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Searched refs:axi (Results 1 – 25 of 34) sorted by relevance

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/third_party/uboot/u-boot-2020.01/arch/arm/mach-sunxi/
Dclock_sun4i.c121 int axi, ahb, apb0; in clock_set_pll1() local
134 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
135 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
138 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
141 axi = axi - 1; in clock_set_pll1()
162 writel(axi << AXI_DIV_SHIFT | in clock_set_pll1()
173 writel(axi << AXI_DIV_SHIFT | in clock_set_pll1()
/third_party/uboot/u-boot-2020.01/arch/arm/dts/
Dimx6qp.dtsi27 clock-names = "axi";
36 clock-names = "axi";
45 clock-names = "axi";
54 clock-names = "axi";
63 clock-names = "ipg", "axi";
72 clock-names = "ipg", "axi";
Dsocfpga_arria10.dtsi428 socfpga_axi_setup: stmmac-axi-config {
450 snps,axi-config = <&socfpga_axi_setup>;
470 snps,axi-config = <&socfpga_axi_setup>;
490 snps,axi-config = <&socfpga_axi_setup>;
Dimx6sx.dtsi1122 clock-names = "disp-axi", "csi_mclk", "dcic";
1131 clock-names = "pxp-axi", "disp-axi";
1141 clock-names = "disp-axi", "csi_mclk", "dcic";
1152 clock-names = "pix", "axi", "disp_axi";
1163 clock-names = "pix", "axi", "disp_axi";
Dimx6sll.dtsi627 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
670 clock-names = "pix", "axi", "disp_axi";
Dimx7ulp.dtsi473 clock-names = "axi", "pix", "disp_axi";
Drk3288.dtsi664 reset-names = "axi", "ahb", "dclk";
708 reset-names = "axi", "ahb", "dclk";
Dstm32mp157c.dtsi1392 stmmac_axi_config_0: stmmac-axi-config {
1417 snps,axi-config = <&stmmac_axi_config_0>;
/third_party/uboot/u-boot-2020.01/drivers/axi/
DMakefile7 obj-$(CONFIG_AXI) += axi-uclass.o
9 obj-$(CONFIG_SANDBOX) += axi-emul-uclass.o
Daxi-uclass.c33 UCLASS_DRIVER(axi) = {
/third_party/boost/libs/histogram/benchmark/
Dplot_benchmarks.py80 for axi in ax.flatten():
81 axi.format_coord = format_coord
99 for axi in ax.flatten():
100 for artist in axi.get_children():
/third_party/uboot/u-boot-2020.01/drivers/pci/
Dpci_tegra.c803 unsigned long fpci, axi, size; local
810 axi = pcie->cs.start;
812 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
823 axi = io->phys_start;
825 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
832 axi = pref->phys_start;
834 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
841 axi = mem->phys_start;
843 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
/third_party/uboot/u-boot-2020.01/arch/mips/dts/
Dimg,boston.dts49 compatible = "xlnx,axi-pcie-host-1.00.a";
78 compatible = "xlnx,axi-pcie-host-1.00.a";
106 compatible = "xlnx,axi-pcie-host-1.00.a";
Dnexys4ddr.dts36 xlnx,s-axi-id-width = <0x1>;
/third_party/uboot/u-boot-2020.01/arch/sandbox/dts/
Dsandbox.dtsi313 axi: axi@0 { label
314 compatible = "sandbox,axi";
Dsandbox64.dts14 axi0 = &axi;
Dsandbox.dts14 axi0 = &axi;
Dtest.dts41 axi0 = &axi;
764 axi: axi@0 { label
765 compatible = "sandbox,axi";
/third_party/uboot/u-boot-2020.01/board/aristainetos/
Daristainetos2.cfg33 #include "axi.cfg"
/third_party/uboot/u-boot-2020.01/test/dm/
DMakefile58 obj-$(CONFIG_AXI) += axi.o
/third_party/uboot/u-boot-2020.01/drivers/
DKconfig11 source "drivers/axi/Kconfig"
DMakefile112 obj-y += axi/
/third_party/uboot/u-boot-2020.01/cmd/
Daxi.c349 U_BOOT_CMD(axi, 7, 1, do_ihs_axi,
DMakefile167 obj-$(CONFIG_CMD_AXI) += axi.o
/third_party/uboot/u-boot-2020.01/arch/arc/dts/
Dhsdk.dts48 "apb-clk", "axi-clk",

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