Home
last modified time | relevance | path

Searched refs:cfg (Results 1 – 25 of 1253) sorted by relevance

12345678910>>...51

/third_party/gettext/os2/
Dconfigure.awk8 cfg["HAVE_ALLOCA"] = 1;
9 cfg["HAVE_ALLOCA_H"] = 1;
10 cfg["HAVE_LONG_FILE_NAMES"] = 1;
11 cfg["STDC_HEADERS"] = 1;
12 cfg["HAVE_GETCWD"] = 1;
13 cfg["HAVE_GETEGID"] = 1;
14 cfg["HAVE_GETEUID"] = 1;
15 cfg["HAVE_GETGID"] = 1;
16 cfg["HAVE_GETPAGESIZE"] = 1;
17 cfg["HAVE_GETUID"] = 1;
[all …]
/third_party/littlefs/bd/
Dlfs_testbd.c13 int lfs_testbd_createcfg(const struct lfs_config *cfg, const char *path, in lfs_testbd_createcfg() argument
23 (void*)cfg, cfg->context, in lfs_testbd_createcfg()
24 (void*)(uintptr_t)cfg->read, (void*)(uintptr_t)cfg->prog, in lfs_testbd_createcfg()
25 (void*)(uintptr_t)cfg->erase, (void*)(uintptr_t)cfg->sync, in lfs_testbd_createcfg()
26 cfg->read_size, cfg->prog_size, cfg->block_size, cfg->block_count, in lfs_testbd_createcfg()
30 lfs_testbd_t *bd = cfg->context; in lfs_testbd_createcfg()
31 bd->cfg = bdcfg; in lfs_testbd_createcfg()
35 bd->power_cycles = bd->cfg->power_cycles; in lfs_testbd_createcfg()
37 if (bd->cfg->erase_cycles) { in lfs_testbd_createcfg()
38 if (bd->cfg->wear_buffer) { in lfs_testbd_createcfg()
[all …]
Dlfs_rambd.c9 int lfs_rambd_createcfg(const struct lfs_config *cfg, in lfs_rambd_createcfg() argument
16 (void*)cfg, cfg->context, in lfs_rambd_createcfg()
17 (void*)(uintptr_t)cfg->read, (void*)(uintptr_t)cfg->prog, in lfs_rambd_createcfg()
18 (void*)(uintptr_t)cfg->erase, (void*)(uintptr_t)cfg->sync, in lfs_rambd_createcfg()
19 cfg->read_size, cfg->prog_size, cfg->block_size, cfg->block_count, in lfs_rambd_createcfg()
21 lfs_rambd_t *bd = cfg->context; in lfs_rambd_createcfg()
22 bd->cfg = bdcfg; in lfs_rambd_createcfg()
25 if (bd->cfg->buffer) { in lfs_rambd_createcfg()
26 bd->buffer = bd->cfg->buffer; in lfs_rambd_createcfg()
28 bd->buffer = lfs_malloc(cfg->block_size * cfg->block_count); in lfs_rambd_createcfg()
[all …]
Dlfs_filebd.c13 int lfs_filebd_createcfg(const struct lfs_config *cfg, const char *path, in lfs_filebd_createcfg() argument
21 (void*)cfg, cfg->context, in lfs_filebd_createcfg()
22 (void*)(uintptr_t)cfg->read, (void*)(uintptr_t)cfg->prog, in lfs_filebd_createcfg()
23 (void*)(uintptr_t)cfg->erase, (void*)(uintptr_t)cfg->sync, in lfs_filebd_createcfg()
24 cfg->read_size, cfg->prog_size, cfg->block_size, cfg->block_count, in lfs_filebd_createcfg()
26 lfs_filebd_t *bd = cfg->context; in lfs_filebd_createcfg()
27 bd->cfg = bdcfg; in lfs_filebd_createcfg()
41 int lfs_filebd_create(const struct lfs_config *cfg, const char *path) { in lfs_filebd_create() argument
47 (void*)cfg, cfg->context, in lfs_filebd_create()
48 (void*)(uintptr_t)cfg->read, (void*)(uintptr_t)cfg->prog, in lfs_filebd_create()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/
Dddr_training_impl.c56 int ddr_training_by_dmc(struct ddr_cfg_st *cfg) in ddr_training_by_dmc() argument
58 if (cfg->cmd_st) { in ddr_training_by_dmc()
60 return ddr_training_cmd_func(cfg); in ddr_training_by_dmc()
63 return ddr_training_boot_func(cfg); in ddr_training_by_dmc()
68 int ddr_training_by_rank(struct ddr_cfg_st *cfg) in ddr_training_by_rank() argument
73 DDR_PHY_SWITCH_RANK(cfg->cur_phy, cfg->rank_idx); in ddr_training_by_rank()
75 for (i = 0; i < cfg->phy[cfg->phy_idx].dmc_num; i++) { in ddr_training_by_rank()
76 cfg->dmc_idx = i; in ddr_training_by_rank()
77 cfg->cur_dmc = cfg->phy[cfg->phy_idx].dmc[i].addr; in ddr_training_by_rank()
78 cfg->cur_pattern = cfg->phy[cfg->phy_idx].dmc[i].ddrt_pattern; in ddr_training_by_rank()
[all …]
Dddr_training_ctl.c34 struct ddr_cfg_st *cfg = &ddr_cfg; in ddr_sw_training_func() local
57 ddr_training_cfg_init(cfg); in ddr_sw_training_func()
81 if (!ddr_training_check_bypass(cfg, DDR_BYPASS_LPCA_MASK) in ddr_sw_training_func()
89 result += ddr_lpca_training(cfg); in ddr_sw_training_func()
98 if (!ddr_training_check_bypass(cfg, DDR_BYPASS_WL_MASK)) { in ddr_sw_training_func()
102 result += ddr_write_leveling(cfg); in ddr_sw_training_func()
110 if (!ddr_training_check_bypass(cfg, DDR_BYPASS_DATAEYE_MASK)) { in ddr_sw_training_func()
111 ddr_training_switch_axi(cfg); in ddr_sw_training_func()
112 ddr_ddrt_init(cfg, DDR_DDRT_MODE_DATAEYE); in ddr_sw_training_func()
113 result += ddr_dataeye_training(cfg); in ddr_sw_training_func()
[all …]
Dddr_training_impl.h211 #define GET_BYTE_NUM(cfg) (cfg->phy[cfg->phy_idx].dmc[cfg->dmc_idx].byte_num) argument
401 int ddr_training_boot_func(struct ddr_cfg_st *cfg);
402 int ddr_training_cmd_func(struct ddr_cfg_st *cfg);
406 void ddr_training_cfg_init(struct ddr_cfg_st *cfg);
407 int ddr_training_by_dmc(struct ddr_cfg_st *cfg);
408 int ddr_training_by_rank(struct ddr_cfg_st *cfg);
409 int ddr_training_by_phy(struct ddr_cfg_st *cfg);
410 int ddr_training_all(struct ddr_cfg_st *cfg);
411 int ddr_dataeye_training_func(struct ddr_cfg_st *cfg);
412 int ddr_vref_training_func(struct ddr_cfg_st *cfg);
[all …]
/third_party/uboot/u-boot-2020.01/drivers/video/
Dssd2828.c153 static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) in read_hw_register() argument
155 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in read_hw_register()
156 return soft_spi_xfer_24bit_3wire(cfg, 0x730000); in read_hw_register()
162 static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, in write_hw_register() argument
165 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in write_hw_register()
166 soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); in write_hw_register()
172 static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) in send_mipi_dcs_command() argument
175 write_hw_register(cfg, SSD2828_PSCR1, 1); in send_mipi_dcs_command()
177 write_hw_register(cfg, SSD2828_PDR, cmdnum); in send_mipi_dcs_command()
183 static void ssd2828_reset(const struct ssd2828_config *cfg) in ssd2828_reset() argument
[all …]
/third_party/flutter/skia/src/sksl/
DSkSLCFGGenerator.cpp296 void CFGGenerator::addExpression(CFG& cfg, std::unique_ptr<Expression>* e, bool constantPropagate) { in addExpression() argument
307 this->addExpression(cfg, &b->fLeft, constantPropagate); in addExpression()
308 BlockId start = cfg.fCurrent; in addExpression()
309 cfg.newBlock(); in addExpression()
310 this->addExpression(cfg, &b->fRight, constantPropagate); in addExpression()
311 cfg.newBlock(); in addExpression()
312 cfg.addExit(start, cfg.fCurrent); in addExpression()
313 cfg.fBlocks[cfg.fCurrent].fNodes.push_back({ in addExpression()
322 this->addExpression(cfg, &b->fRight, constantPropagate); in addExpression()
323 this->addLValue(cfg, &b->fLeft); in addExpression()
[all …]
/third_party/libnl/lib/route/cls/ematch/
Dtext.c28 struct tcf_em_text cfg; member
36 t->cfg.from_offset = offset; in rtnl_ematch_text_set_from()
37 t->cfg.from_layer = layer; in rtnl_ematch_text_set_from()
42 return ((struct text_data *) rtnl_ematch_data(e))->cfg.from_offset; in rtnl_ematch_text_get_from_offset()
47 return ((struct text_data *) rtnl_ematch_data(e))->cfg.from_layer; in rtnl_ematch_text_get_from_layer()
54 t->cfg.to_offset = offset; in rtnl_ematch_text_set_to()
55 t->cfg.to_layer = layer; in rtnl_ematch_text_set_to()
60 return ((struct text_data *) rtnl_ematch_data(e))->cfg.to_offset; in rtnl_ematch_text_get_to_offset()
65 return ((struct text_data *) rtnl_ematch_data(e))->cfg.to_layer; in rtnl_ematch_text_get_to_layer()
77 t->cfg.pattern_len = len; in rtnl_ematch_text_set_pattern()
[all …]
/third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/hal/ctrl/hisiv200/
Dhdmi_hal_ddc.c167 static hi_s32 ddc_cmd_issue(const ddc_cfg *cfg, hi_bool read_issue) in ddc_cmd_issue() argument
173 hdmi_if_null_return(cfg, HI_FAILURE); in ddc_cmd_issue()
174 segment = cfg->segment; in ddc_cmd_issue()
175 offset = cfg->offset; in ddc_cmd_issue()
176 data_size = cfg->data_size; in ddc_cmd_issue()
178 switch (cfg->func_type) { in ddc_cmd_issue()
191 if (cfg->master_mode == DDC_MASTER_MODE_PWD) { in ddc_cmd_issue()
198 hdmi_pwd_mst_cmd_set(cfg->issue_mode); in ddc_cmd_issue()
278 static hi_s32 ddc_data_issue(ddc_cfg *cfg, hi_bool read_issue) in ddc_data_issue() argument
282 …timeout = cfg->issue_timeout < DDC_DEFAULT_TIMEOUT_ISSUE ? DDC_DEFAULT_TIMEOUT_ISSUE : cfg->sda_ti… in ddc_data_issue()
[all …]
/third_party/skia/third_party/externals/tint/src/transform/
Dvertex_pulling_test.cc49 VertexPulling::Config cfg; in TEST_F() local
50 cfg.entry_point_name = "_"; in TEST_F()
53 data.Add<VertexPulling::Config>(cfg); in TEST_F()
67 VertexPulling::Config cfg; in TEST_F() local
68 cfg.entry_point_name = "main"; in TEST_F()
71 data.Add<VertexPulling::Config>(cfg); in TEST_F()
89 VertexPulling::Config cfg; in TEST_F() local
90 cfg.vertex_state = { in TEST_F()
92 cfg.entry_point_name = "main"; in TEST_F()
95 data.Add<VertexPulling::Config>(cfg); in TEST_F()
[all …]
Darray_length_from_uniform_test.cc91 ArrayLengthFromUniform::Config cfg({0, 30u}); in TEST_F() local
92 cfg.bindpoint_to_size_index.emplace(sem::BindingPoint{0, 0}, 0); in TEST_F()
95 data.Add<ArrayLengthFromUniform::Config>(std::move(cfg)); in TEST_F()
144 ArrayLengthFromUniform::Config cfg({0, 30u}); in TEST_F() local
145 cfg.bindpoint_to_size_index.emplace(sem::BindingPoint{0, 0}, 0); in TEST_F()
148 data.Add<ArrayLengthFromUniform::Config>(std::move(cfg)); in TEST_F()
261 ArrayLengthFromUniform::Config cfg({0, 30u}); in TEST_F() local
262 cfg.bindpoint_to_size_index.emplace(sem::BindingPoint{0, 2u}, 0); in TEST_F()
263 cfg.bindpoint_to_size_index.emplace(sem::BindingPoint{1u, 2u}, 1); in TEST_F()
264 cfg.bindpoint_to_size_index.emplace(sem::BindingPoint{2u, 2u}, 2); in TEST_F()
[all …]
Dsingle_entry_point_test.cc60 SingleEntryPoint::Config cfg("_"); in TEST_F() local
63 data.Add<SingleEntryPoint::Config>(cfg); in TEST_F()
79 SingleEntryPoint::Config cfg("foo"); in TEST_F() local
82 data.Add<SingleEntryPoint::Config>(cfg); in TEST_F()
95 SingleEntryPoint::Config cfg("main"); in TEST_F() local
98 data.Add<SingleEntryPoint::Config>(cfg); in TEST_F()
130 SingleEntryPoint::Config cfg("comp_main1"); in TEST_F() local
133 data.Add<SingleEntryPoint::Config>(cfg); in TEST_F()
180 SingleEntryPoint::Config cfg("comp_main1"); in TEST_F() local
183 data.Add<SingleEntryPoint::Config>(cfg); in TEST_F()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/video/exynos/
Dexynos_fb.c105 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
108 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
112 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
116 writel(cfg, &reg->dualrgb); in exynos_fimd_set_dualrgb()
123 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
126 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
128 writel(cfg, &reg->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
135 unsigned int cfg = 0; in exynos_fimd_set_par() local
138 cfg = readl((unsigned int)&reg->wincon0 + in exynos_fimd_set_par()
141 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
[all …]
/third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/hal/ctrl/hisiv100/
Dhdmi_hal_ddc.c164 static hi_s32 ddc_cmd_issue(const ddc_cfg *cfg, hi_bool read_issue) in ddc_cmd_issue() argument
169 hdmi_if_null_return(cfg, HI_FAILURE); in ddc_cmd_issue()
170 segment = cfg->segment; in ddc_cmd_issue()
171 offset = cfg->offset; in ddc_cmd_issue()
172 data_size = cfg->data_size; in ddc_cmd_issue()
173 switch (cfg->func_type) { in ddc_cmd_issue()
187 if (cfg->master_mode == DDC_MASTER_MODE_PWD) { in ddc_cmd_issue()
194 hdmi_pwd_mst_cmd_set(cfg->issue_mode); in ddc_cmd_issue()
196 hdmi_err("invalid master_mode=%u\n", cfg->master_mode); in ddc_cmd_issue()
275 static hi_s32 ddc_data_issue(ddc_cfg *cfg, hi_bool read_issue) in ddc_data_issue() argument
[all …]
/third_party/uboot/u-boot-2020.01/include/linux/
Dkconfig.h20 #define config_enabled(cfg) _config_enabled(cfg) argument
59 #define config_val(cfg) _config_val(_IS_TPL, cfg) argument
60 #define _config_val(x, cfg) __config_val(x, cfg) argument
61 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) argument
62 #define ___config_val(arg1_or_junk, cfg) \ argument
63 ____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
66 #define config_val(cfg) _config_val(_IS_SPL, cfg) argument
67 #define _config_val(x, cfg) __config_val(x, cfg) argument
68 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) argument
69 #define ___config_val(arg1_or_junk, cfg) \ argument
[all …]
/third_party/uboot/u-boot-2020.01/drivers/power/
Daxp209.c35 u8 cfg, current; in axp_set_dcdc2() local
45 cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); in axp_set_dcdc2()
49 current != cfg) { in axp_set_dcdc2()
50 if (current < cfg) in axp_set_dcdc2()
65 u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); in axp_set_dcdc3() local
72 rc = pmic_bus_write(AXP209_DCDC3_VOLTAGE, cfg); in axp_set_dcdc3()
82 u8 cfg, reg; in axp_set_aldo2() local
88 cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100); in axp_set_aldo2()
94 reg |= AXP209_LDO24_LDO2_SET(reg, cfg); in axp_set_aldo2()
104 u8 cfg; in axp_set_aldo3() local
[all …]
Daxp818.c32 u8 cfg = axp818_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
38 ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg); in axp_set_dcdc1()
49 u8 cfg; in axp_set_dcdc2() local
52 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); in axp_set_dcdc2()
54 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); in axp_set_dcdc2()
60 ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg); in axp_set_dcdc2()
71 u8 cfg; in axp_set_dcdc3() local
74 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); in axp_set_dcdc3()
76 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); in axp_set_dcdc3()
82 ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg); in axp_set_dcdc3()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/ddr/altera/
Dsdram_gen5.c56 static int get_errata_rows(const struct socfpga_sdram_config *cfg) in get_errata_rows() argument
62 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in get_errata_rows()
65 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> in get_errata_rows()
68 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> in get_errata_rows()
71 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> in get_errata_rows()
285 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) in sdr_get_ctrlcfg() argument
288 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in sdr_get_ctrlcfg()
291 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> in sdr_get_ctrlcfg()
294 u32 ctrl_cfg = cfg->ctrl_cfg; in sdr_get_ctrlcfg()
323 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) in sdr_get_addr_rw() argument
[all …]
/third_party/uboot/u-boot-2020.01/drivers/pinctrl/renesas/
Dsh_pfc.h411 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
412 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
415 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
416 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
417 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
418 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
419 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
422 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
423 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
424 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
[all …]
/third_party/uboot/u-boot-2020.01/include/fsl-mc/
Dfsl_dpni.h51 #define DPNI_PREP_CFG(param, cfg) \ argument
53 MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \
54 MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \
55 MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \
56 MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \
57 MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \
58 MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \
59 MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \
63 #define DPNI_EXT_CFG(param, cfg) \ argument
65 MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \
[all …]
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/default/cmd_bin/
Dddr_training_cmd.c150 static void ddr_training_result_init(struct ddr_cfg_st *cfg, struct ddr_training_result_st *ddrtr_r… in ddr_training_result_init() argument
155 ddrtr_res->phy_num = cfg->phy_num; in ddr_training_result_init()
156 for (i = 0; i < cfg->phy_num; i++) { in ddr_training_result_init()
157 ddrtr_res->phy_st[i].rank_num = cfg->phy[i].rank_num; in ddr_training_result_init()
159 for (j = 0; j < cfg->phy[i].rank_num; j++) { in ddr_training_result_init()
160 ddrtr_res->phy_st[i].rank_st[j].item = cfg->phy[i].rank[j].item; in ddr_training_result_init()
161 ddrtr_res->phy_st[i].rank_st[j].ddrtr_data.base_phy = cfg->phy[i].addr; in ddr_training_result_init()
162 ddrtr_res->phy_st[i].rank_st[j].ddrtr_data.byte_num = cfg->phy[i].total_byte_num; in ddr_training_result_init()
169 void ddr_result_data_save(struct ddr_cfg_st *cfg, struct training_data *training) in ddr_result_data_save() argument
174 struct ddr_training_result_st *ddrtr_res = (struct ddr_training_result_st *)cfg->res_st; in ddr_result_data_save()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/adc/
Dexynos-adc.c40 unsigned int cfg; in exynos_adc_start_channel() local
43 cfg = readl(&regs->con2); in exynos_adc_start_channel()
44 cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK; in exynos_adc_start_channel()
45 cfg |= ADC_V2_CON2_CHAN_SEL(channel); in exynos_adc_start_channel()
46 writel(cfg, &regs->con2); in exynos_adc_start_channel()
49 cfg = readl(&regs->con1); in exynos_adc_start_channel()
50 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
61 unsigned int cfg; in exynos_adc_stop() local
64 cfg = readl(&regs->con1); in exynos_adc_stop()
65 cfg &= ~ADC_V2_CON1_STC_EN; in exynos_adc_stop()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/ls102xa/
Dfsl_ls1_serdes.c43 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane() local
49 cfg &= RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()
50 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()
55 cfg &= RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
56 cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT; in serdes_get_first_lane()
64 if (unlikely(cfg == 0)) in serdes_get_first_lane()
68 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
79 u32 cfg; in serdes_init() local
82 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
83 cfg >>= sd_prctl_shift; in serdes_init()
[all …]

12345678910>>...51