| /third_party/uboot/u-boot-2020.01/drivers/serial/ |
| D | serial_uniphier.c | 97 unsigned int clk_rate; member
101 { .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 },
102 { .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 },
103 { .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 },
104 { .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 },
105 { .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 },
106 { .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 },
107 { .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 },
108 { .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 },
109 { .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 },
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| D | atmel_usart.c | 236 ulong clk_rate; in atmel_serial_enable_clk() local
249 clk_rate = clk_get_rate(&clk); in atmel_serial_enable_clk()
250 if (!clk_rate) in atmel_serial_enable_clk()
253 priv->usart_clk_rate = clk_rate; in atmel_serial_enable_clk()
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| /third_party/uboot/u-boot-2020.01/drivers/clk/ |
| D | clk_versal.c | 477 static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate) in versal_clock_pll() argument
483 *clk_rate = versal_clock_get_pll_rate(clk_id); in versal_clock_pll()
493 u64 clk_rate; in versal_clock_calc() local
496 if (versal_clock_pll(clk_id, &clk_rate)) in versal_clock_calc()
497 return clk_rate; in versal_clock_calc()
504 clk_rate = versal_clock_calc(parent_id); in versal_clock_calc()
508 clk_rate = DIV_ROUND_CLOSEST(clk_rate, div); in versal_clock_calc()
511 return clk_rate; in versal_clock_calc()
514 static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) in versal_clock_get_rate() argument
518 *clk_rate = versal_clock_ref(clk_id); in versal_clock_get_rate()
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| D | clk-composite.c | 53 struct clk *clk_rate = composite->rate; in clk_composite_set_rate() local
55 return rate_ops->set_rate(clk_rate, rate); in clk_composite_set_rate()
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| /third_party/uboot/u-boot-2020.01/drivers/clk/at91/ |
| D | clk-plladiv.c | 24 ulong clk_rate; in at91_plladiv_clk_get_rate() local
31 clk_rate = clk_get_rate(&source); in at91_plladiv_clk_get_rate()
33 clk_rate /= 2; in at91_plladiv_clk_get_rate()
35 return clk_rate; in at91_plladiv_clk_get_rate()
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| D | clk-peripheral.c | 84 ulong clk_rate; in periph_get_rate() local
93 clk_rate = clk_get_rate(&clk_dev); in periph_get_rate()
97 return clk_rate; in periph_get_rate()
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| D | clk-utmi.c | 27 ulong clk_rate; in utmi_clk_enable() local
45 clk_rate = clk_get_rate(&clk_dev); in utmi_clk_enable()
46 switch (clk_rate) { in utmi_clk_enable()
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| D | clk-generated.c | 53 ulong clk_rate; in generic_clk_get_rate() local
69 clk_rate = clk_get_rate(&parent) / (gckdiv + 1); in generic_clk_get_rate()
73 return clk_rate; in generic_clk_get_rate()
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| /third_party/uboot/u-boot-2020.01/drivers/timer/ |
| D | atmel_pit_timer.c | 44 ulong clk_rate; in atmel_pit_probe() local
51 clk_rate = clk_get_rate(&clk); in atmel_pit_probe()
52 if (!clk_rate) in atmel_pit_probe()
55 uc_priv->clock_rate = clk_rate / 16; in atmel_pit_probe()
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| /third_party/uboot/u-boot-2020.01/drivers/phy/ |
| D | phy-stm32-usbphyc.c | 64 static void stm32_usbphyc_get_pll_params(u32 clk_rate, in stm32_usbphyc_get_pll_params() argument
81 do_div(ndiv, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
85 do_div(frac, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
93 u32 clk_rate = clk_get_rate(&usbphyc->clk); in stm32_usbphyc_pll_init() local
96 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) { in stm32_usbphyc_pll_init()
98 __func__, clk_rate); in stm32_usbphyc_pll_init()
102 stm32_usbphyc_get_pll_params(clk_rate, &pll_params); in stm32_usbphyc_pll_init()
116 clk_rate, pll_params.ndiv, pll_params.frac); in stm32_usbphyc_pll_init()
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| /third_party/uboot/u-boot-2020.01/drivers/adc/ |
| D | rockchip-saradc.c | 32 unsigned long clk_rate; member
109 ret = clk_set_rate(&clk, priv->data->clk_rate); in rockchip_saradc_probe()
149 .clk_rate = 1000000,
155 .clk_rate = 50000,
161 .clk_rate = 1000000,
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| /third_party/uboot/u-boot-2020.01/drivers/watchdog/ |
| D | orion_wdt.c | 32 unsigned long clk_rate; member
51 writel(priv->clk_rate * priv->timeout, in orion_wdt_reset()
70 writel(priv->clk_rate * priv->timeout, in orion_wdt_start()
164 priv->clk_rate = clk_get_rate(&priv->clk); in orion_wdt_probe()
166 priv->clk_rate = 25000000; in orion_wdt_probe()
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| D | bcm6345_wdt.c | 30 unsigned long clk_rate; member
46 u32 val = priv->clk_rate / 1000 * timeout; in bcm6345_wdt_start()
100 priv->clk_rate = clk_get_rate(&clk); in bcm6345_wdt_probe()
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| D | armada-37xx-wdt.c | 20 ulong clk_rate; member
128 priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN; in a37xx_wdt_start()
166 priv->clk_rate = (ulong)get_ref_clk() * 1000000; in a37xx_wdt_probe()
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/imx8/ |
| D | misc.c | 6 int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) in sc_pm_setup_uart() argument
8 sc_pm_clock_rate_t rate = clk_rate; in sc_pm_setup_uart()
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| /third_party/uboot/u-boot-2020.01/drivers/video/ |
| D | atmel_hlcdfb.c | 259 ulong clk_rate; member
266 ulong clk_rate; in at91_hlcdc_enable_clk() local
277 clk_rate = clk_get_rate(&clk); in at91_hlcdc_enable_clk()
278 if (!clk_rate) { in at91_hlcdc_enable_clk()
283 priv->clk_rate = clk_rate; in at91_hlcdc_enable_clk()
326 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
327 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
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| /third_party/uboot/u-boot-2020.01/drivers/i2c/ |
| D | meson_i2c.c | 230 ulong clk_rate; in meson_i2c_set_bus_speed() local
233 clk_rate = clk_get_rate(&i2c->clk); in meson_i2c_set_bus_speed()
234 if (IS_ERR_VALUE(clk_rate)) in meson_i2c_set_bus_speed()
237 div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor); in meson_i2c_set_bus_speed()
251 debug("meson i2c: set clk %u, src %lu, div %u\n", speed, clk_rate, div); in meson_i2c_set_bus_speed()
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| D | at91_i2c.c | 181 ulong clk_rate; in at91_i2c_enable_clk() local
192 clk_rate = clk_get_rate(&clk); in at91_i2c_enable_clk()
193 if (!clk_rate) in at91_i2c_enable_clk()
196 bus->bus_clk_rate = clk_rate; in at91_i2c_enable_clk()
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| /third_party/uboot/u-boot-2020.01/product/hii2c/ |
| D | i2c_hibvt.c | 388 unsigned int clk_rate; in hibvt_i2c_set_freq() local
392 clk_rate = i2c->clk; in hibvt_i2c_set_freq()
393 max_freq = clk_rate >> 1; in hibvt_i2c_set_freq()
407 val = clk_rate / (freq * 2); in hibvt_i2c_set_freq()
412 val = (clk_rate * 36) / (freq * 100); in hibvt_i2c_set_freq()
415 val = (clk_rate * 64) / (freq * 100); in hibvt_i2c_set_freq()
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| /third_party/uboot/u-boot-2020.01/drivers/spi/ |
| D | atcspi200_spi.c | 345 ulong clk_rate; in atcspi200_spi_get_clk() local
352 clk_rate = clk_get_rate(&clk); in atcspi200_spi_get_clk()
353 if (!clk_rate) in atcspi200_spi_get_clk()
356 ns->clock = clk_rate; in atcspi200_spi_get_clk()
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| D | atmel_spi.c | 438 ulong clk_rate; in atmel_spi_enable_clk() local
449 clk_rate = clk_get_rate(&clk); in atmel_spi_enable_clk()
450 if (!clk_rate) in atmel_spi_enable_clk()
453 priv->bus_clk_rate = clk_rate; in atmel_spi_enable_clk()
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| D | bcm63xx_hsspi.c | 98 ulong clk_rate; member
145 set = DIV_ROUND_UP(priv->clk_rate, priv->speed); in bcm63xx_hsspi_activate_cs()
364 priv->clk_rate = clk_get_rate(&clk); in bcm63xx_hsspi_probe()
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| /third_party/uboot/u-boot-2020.01/drivers/mtd/nand/raw/ |
| D | denali_dt.c | 121 denali->clk_rate = clk_get_rate(&clk); in denali_dt_probe()
130 denali->clk_rate = 50000000; in denali_dt_probe()
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| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-imx8/ |
| D | sys_proto.h | 23 int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
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| /third_party/uboot/u-boot-2020.01/drivers/mmc/ |
| D | msm_sdhci.c | 53 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency", in msm_sdc_clk_init() local
78 ret = clk_set_rate(&clk, clk_rate); in msm_sdc_clk_init()
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