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Searched refs:cs_num (Results 1 – 18 of 18) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/a38x/
Dmv_ddr_topology.c201 unsigned int cs_num = 0; in mv_ddr_cs_num_get() local
214 cs_num++; in mv_ddr_cs_num_get()
217 return cs_num; in mv_ddr_cs_num_get()
302 unsigned int cs_num = mv_ddr_cs_num_get(); in mv_ddr_rtt_park_get() local
305 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_rtt_park_get()
306 rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1]; in mv_ddr_rtt_park_get()
319 unsigned int cs_num = mv_ddr_cs_num_get(); in mv_ddr_rtt_wr_get() local
322 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_rtt_wr_get()
323 rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1]; in mv_ddr_rtt_wr_get()
Dddr3_training_hw_algo.c45 u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0x1f; in ddr3_tip_write_additional_odt_setting() local
63 for (cs_num = 0; cs_num < max_cs; cs_num++) { in ddr3_tip_write_additional_odt_setting()
64 read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num); in ddr3_tip_write_additional_odt_setting()
67 if (read_sample[cs_num] >= max_read_sample) { in ddr3_tip_write_additional_odt_setting()
68 if (read_sample[cs_num] == max_read_sample) in ddr3_tip_write_additional_odt_setting()
71 max_read_sample = read_sample[cs_num]; in ddr3_tip_write_additional_odt_setting()
80 RL_PHY_REG(cs_num), in ddr3_tip_write_additional_odt_setting()
90 if (read_sample[cs_num] < min_read_sample) in ddr3_tip_write_additional_odt_setting()
91 min_read_sample = read_sample[cs_num]; in ddr3_tip_write_additional_odt_setting()
117 u32 cs_num; in get_valid_win_rx() local
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Dddr3_init.c108 u32 cs_num; in mv_ddr_training_params_set() local
110 cs_num = mv_ddr_cs_num_get(); in mv_ddr_training_params_set()
126 if (cs_num == 1) { in mv_ddr_training_params_set()
Dddr3_training.c12 #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) argument
279 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
290 SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)), in ddr3_tip_configure_cs()
291 0x3 << (cs_num * 4))); in ddr3_tip_configure_cs()
298 (addr_hi << (2 + cs_num * 4)), in ddr3_tip_configure_cs()
299 0x3 << (2 + cs_num * 4))); in ddr3_tip_configure_cs()
305 data_high << (20 + cs_num), 1 << (20 + cs_num))); in ddr3_tip_configure_cs()
310 SDRAM_ADDR_CTRL_REG, 1 << (16 + cs_num), in ddr3_tip_configure_cs()
311 1 << (16 + cs_num))); in ddr3_tip_configure_cs()
313 switch (cs_num) { in ddr3_tip_configure_cs()
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Dddr3_training_pbs.c48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
83 pbs_pattern, search_edge, CS_SINGLE, cs_num, in ddr3_tip_pbs()
214 search_edge, CS_SINGLE, cs_num, in ddr3_tip_pbs()
397 CS_SINGLE, cs_num, train_status); in ddr3_tip_pbs()
526 cs_num, train_status); in ddr3_tip_pbs()
623 search_edge, CS_SINGLE, cs_num, in ddr3_tip_pbs()
940 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode) in ddr3_tip_print_pbs_result() argument
944 PBS_RX_PHY_REG(cs_num, 0) : in ddr3_tip_print_pbs_result()
945 PBS_TX_PHY_REG(cs_num , 0); in ddr3_tip_print_pbs_result()
950 (pbs_mode == PBS_RX_MODE) ? "Rx" : "Tx", cs_num); in ddr3_tip_print_pbs_result()
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Dddr3_training_ip_bist.h43 u32 offset, u32 cs_num, u32 pattern_addr_length);
45 u32 cs_num);
Dddr3_training_ip_engine.h61 enum hws_ddr_cs cs_type, u32 cs_num,
75 enum hws_ddr_cs train_cs_type, u32 cs_num,
Dddr3_training_bist.c26 u32 offset, u32 cs_num, u32 pattern_addr_length) in ddr3_tip_bist_activate() argument
55 rd_mode, cs_num, addr_stress_jump, duration); in ddr3_tip_bist_activate()
119 u32 cs_num) in hws_ddr3_run_bist() argument
129 hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base); in hws_ddr3_run_bist()
135 cs_num, 15); in hws_ddr3_run_bist()
146 cs_num, 15); in hws_ddr3_run_bist()
Dddr3_training_ip_engine.c345 enum hws_ddr_cs cs_type, u32 cs_num, in ddr3_tip_ip_training() argument
393 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26, in ddr3_tip_ip_training()
628 u32 delay_between_burst, u32 rd_mode, u32 cs_num, in ddr3_tip_configure_odpg() argument
636 (rx_phases << 21) | (rd_mode << 25) | (cs_num << 26) | in ddr3_tip_configure_odpg()
968 enum hws_ddr_cs train_cs_type, u32 cs_num, in ddr3_tip_ip_training_wrapper_int() argument
1023 pattern, edge_comp_used, train_cs_type, cs_num)); in ddr3_tip_ip_training_wrapper_int()
1030 cs_num, train_status); in ddr3_tip_ip_training_wrapper_int()
1042 cs_num = 0; in ddr3_tip_ip_training_wrapper_int()
1105 enum hws_ddr_cs train_cs_type, u32 cs_num, in ddr3_tip_ip_training_wrapper() argument
1144 train_cs_type, cs_num, train_status); in ddr3_tip_ip_training_wrapper()
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Dddr3_training_ip.h112 u8 cs_num; member
Dddr3_training_ip_flow.h110 u32 delay_between_burst, u32 rd_mode, u32 cs_num,
Dddr3_training_ip_prv_if.h78 enum hws_bist_operation oper_type, u32 offset, u32 cs_num,
Dddr3_init.h179 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
/third_party/uboot/u-boot-2020.01/drivers/spi/
Dmscc_bb_spi.c22 int cs_num; member
37 priv->cs_num = cs; in mscc_bb_spi_cs_activate()
69 debug("Activated CS%d\n", priv->cs_num); in mscc_bb_spi_cs_activate()
99 debug("Deactivated CS%d\n", priv->cs_num); in mscc_bb_spi_cs_deactivate()
/third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/axp/
Dddr3_sdram.c494 u32 chan, byte_count, cs_num, byte; in ddr3_dram_sram_burst() local
510 cs_num = (src / (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
512 ((cs_num << 1) | (1 << 0))); in ddr3_dram_sram_burst()
517 cs_num = (dst / (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
519 ((cs_num << 25) | (1 << 24))); in ddr3_dram_sram_burst()
Dddr3_spd.c581 u32 cs, cl, cs_num, cs_ena; local
638 cs_num = 0;
640 cs_num = ddr3_get_cs_num_from_reg();
644 cs_num += dimm_info[dimm].num_of_module_ranks;
646 if (cs_num > MAX_CS) {
687 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
1071 if (cs_num > 1)
/third_party/ffmpeg/libavcodec/
Dopusenc_psy.h61 int cs_num; member
Dopusenc_psy.c509 s->cs_num = 0; in ff_opus_psy_postencode_update()