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/third_party/node/test/parallel/
Dtest-error-serdes.js8 function cycle(err) { function
12 assert.strictEqual(cycle(0), 0);
13 assert.strictEqual(cycle(-1), -1);
14 assert.strictEqual(cycle(1.4), 1.4);
15 assert.strictEqual(cycle(null), null);
16 assert.strictEqual(cycle(undefined), undefined);
17 assert.strictEqual(cycle('foo'), 'foo');
28 err = cycle(err);
32 assert.strictEqual(cycle(new RangeError('foo')).name, 'RangeError');
33 assert.strictEqual(cycle(new TypeError('foo')).name, 'TypeError');
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/third_party/ffmpeg/libavfilter/
Dvf_dejudder.c66 int cycle; member
74 OFFSET(cycle), AV_OPT_TYPE_INT, {.i64 = 4}, 2, 240, .flags = FLAGS},
86 outlink->time_base = av_mul_q(inlink->time_base, av_make_q(1, 2 * s->cycle)); in config_out_props()
87 outlink->frame_rate = av_mul_q(inlink->frame_rate, av_make_q(2 * s->cycle, 1)); in config_out_props()
89 av_log(ctx, AV_LOG_VERBOSE, "cycle:%d\n", s->cycle); in config_out_props()
98 s->ringbuff = av_mallocz_array(s->cycle+2, sizeof(*s->ringbuff)); in dejudder_init()
107 s->start_count = s->cycle + 2; in dejudder_init()
134 s->new_pts = next_pts * 2 * s->cycle; in filter_frame()
138 for (k = 0; k < s->cycle + 2; k++) in filter_frame()
141 s->new_pts += (s->cycle - 1) * (judbuff[s->i3] - judbuff[s->i1]) in filter_frame()
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Dvf_decimate.c55 int cycle; member
69 …{ "cycle", "set the number of frame from which one will be dropped", OFFSET(cycle), AV_OPT_TYP…
179 if (++dm->fid != dm->cycle) in filter_frame()
187 for (i = 0; i < dm->cycle; i++) { in filter_frame()
200 av_log(ctx, AV_LOG_DEBUG, "1/%d frame drop:\n", dm->cycle); in filter_frame()
201 for (i = 0; i < dm->cycle && dm->queue[i].frame; i++) { in filter_frame()
213 for (i = 0; i < dm->cycle && dm->queue[i].frame; i++) { in filter_frame()
258 dm->queue = av_calloc(dm->cycle, sizeof(*dm->queue)); in config_input()
264 dm->clean_src = av_calloc(dm->cycle, sizeof(*dm->clean_src)); in config_input()
320 for (i = 0; i < dm->cycle; i++) in decimate_uninit()
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/third_party/node/deps/npm/test/tap/
Dsymlink-cycle.js10 var cycle = path.join(base, 'cycle') variable
28 mkdirp.sync(path.join(cycle, 'node_modules'))
30 path.join(cycle, 'package.json'),
33 fs.symlinkSync(cycle, path.join(cycle, 'node_modules', 'cycle'), 'junction')
38 process.chdir(cycle)
/third_party/boost/libs/fiber/performance/thread/
Dbuffered_channel.hpp44 std::atomic< std::size_t > cycle{ 0 }; member
67 …return 0 > static_cast< std::intptr_t >( slots_[idx & (capacity_ - 1)].cycle.load( std::memory_ord… in is_full_()
72 …return 0 > static_cast< std::intptr_t >( slots_[idx & (capacity_ - 1)].cycle.load( std::memory_ord… in is_empty_()
81 std::size_t cycle{ s->cycle.load( std::memory_order_acquire) }; in try_push_() local
82 … std::intptr_t diff{ static_cast< std::intptr_t >( cycle) - static_cast< std::intptr_t >( idx) }; in try_push_()
94 s->cycle.store( idx + 1, std::memory_order_release); in try_push_()
102 std::size_t cycle = s->cycle.load( std::memory_order_acquire); in try_value_pop_() local
103 …std::intptr_t diff{ static_cast< std::intptr_t >( cycle) - static_cast< std::intptr_t >( idx + 1) … in try_value_pop_()
125 s->cycle.store( idx + capacity_, std::memory_order_release); in try_pop_()
138 slots_[i].cycle.store( i, std::memory_order_relaxed);
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/third_party/boost/libs/graph/example/
Dvisitor.expected16 cycle: 1 --> 1
17 cycle: 1 --> 3
18 cycle: 3 --> 1
20 cycle: 4 --> 0
21 cycle: 4 --> 1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp117 int cycle = Stalls; in getHazardType() local
134 int StageCycle = cycle + (int)i; in getHazardType()
165 cycle += IS->getNextCycles(); in getHazardType()
184 unsigned cycle = 0; in EmitInstruction() local
193 assert(((cycle + i) < RequiredScoreboard.getDepth()) && in EmitInstruction()
200 freeUnits &= ~ReservedScoreboard[cycle + i]; in EmitInstruction()
204 freeUnits &= ~RequiredScoreboard[cycle + i]; in EmitInstruction()
216 RequiredScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
218 ReservedScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
222 cycle += IS->getNextCycles(); in EmitInstruction()
/third_party/littlefs/tests/
Dtest_exhaustion.toml19 uint32_t cycle = 0;
25 srand(cycle * i);
54 srand(cycle * i);
69 cycle += 1;
82 LFS_WARN("completed %d cycles", cycle);
101 uint32_t cycle = 0;
107 srand(cycle * i);
136 srand(cycle * i);
151 cycle += 1;
164 LFS_WARN("completed %d cycles", cycle);
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/third_party/gstreamer/gstplugins_good/gst/goom/
Dtentacle3d.c39 float cycle; member
79 data->cycle = 0.0f; in tentacle_fx_init()
229 pretty_move (PluginInfo * goomInfo, float cycle, float *dist, float *dist2, in pretty_move() argument
249 tmp = 30 + D - 90.0f * (1.0f + sin (cycle * 19 / 20)); in pretty_move()
256 tmp = G_PI * sin (cycle) / 32 + 3 * G_PI / 2; in pretty_move()
262 cycle *= 2.0f * G_PI; in pretty_move()
264 cycle *= -1.0f * G_PI; in pretty_move()
265 tmp = cycle - (G_PI * 2.0) * floor (cycle / (G_PI * 2.0)); in pretty_move()
332 pretty_move (goomInfo, fx_data->cycle, &dist, &dist2, &rotangle, fx_data); in tentacle_update()
345 fx_data->cycle += 0.01f; in tentacle_update()
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/third_party/uboot/u-boot-2020.01/arch/mips/mach-ath79/ar934x/
Dddr.c42 u32 reg, cycle, ctl; in ar934x_ddr_init() local
51 cycle = 0xffff; in ar934x_ddr_init()
57 cycle = 0xff; in ar934x_ddr_init()
59 cycle = 0xffff; in ar934x_ddr_init()
63 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
80 cycle = 0xffffffff; in ar934x_ddr_init()
147 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in ar934x_ddr_init()
/third_party/boost/libs/thread/example/
Dperf_shared_mutex.cpp27 int cycle(0); in shared() local
28 while (++cycle < cycles) in shared()
36 int cycle(0); in unique() local
37 while (++cycle < cycles) in unique()
/third_party/boost/boost/geometry/algorithms/detail/overlay/
Dcheck_enrich.hpp74 int op_index, int cycle, int start, operation_type for_operation, in check_detailed() argument
96 … check_detailed(meta_turns, meta_turns[ip_index], op_index, cycle, start, for_operation, error); in check_detailed()
107 … check_detailed(meta_turns, meta_turns[ip_index], other_index, cycle, start, for_operation, error); in check_detailed()
141 int cycle = 0; in check_graph() local
155 std::cout << "CYCLE " << cycle << std::endl; in check_graph()
158 check_detailed(meta_turns, *it, i, cycle++, it->index, for_operation, error); in check_graph()
/third_party/nghttp2/src/
Dshrpx_worker.h118 uint32_t cycle; member
146 uint32_t cycle; member
152 auto d = lhs.cycle - rhs.cycle; in operator()
166 uint32_t cycle; member
175 uint32_t cycle; member
181 auto d = lhs.cycle - rhs.cycle; in operator()
Dshrpx_worker.cc175 uint32_t cycle; in ensure_enqueue_addr() local
178 cycle = top.cycle; in ensure_enqueue_addr()
180 cycle = 0; in ensure_enqueue_addr()
183 addr->cycle = cycle; in ensure_enqueue_addr()
185 wg->pq.push(DownstreamAddrEntry{addr, addr->seq, addr->cycle}); in ensure_enqueue_addr()
191 cycle = top.cycle; in ensure_enqueue_addr()
193 cycle = 0; in ensure_enqueue_addr()
196 wg->cycle = cycle; in ensure_enqueue_addr()
198 wgpq.push(WeightGroupEntry{wg, wg->seq, wg->cycle}); in ensure_enqueue_addr()
342 wg->pq.push(DownstreamAddrEntry{&addr, addr.seq, addr.cycle}); in replace_downstream_config()
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/third_party/boost/libs/hana/test/_include/laws/
Dmonad_plus.hpp326 cycle(list(), size_c<0>),
330 cycle(list(), size_c<1>),
334 cycle(list(), size_c<2>),
338 cycle(list(), size_c<3>),
344 cycle(list(eq<0>{}), size_c<0>),
348 cycle(list(eq<0>{}), size_c<1>),
352 cycle(list(eq<0>{}), size_c<2>),
356 cycle(list(eq<0>{}), size_c<3>),
362 cycle(list(eq<0>{}, eq<1>{}), size_c<0>),
366 cycle(list(eq<0>{}, eq<1>{}), size_c<1>),
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/third_party/boost/libs/serialization/doc/
Dprofile1.txt93 cycle, the cycle number is printed between the
112 member of a cycle, the cycle number is printed between
134 member of a cycle, the cycle number is printed
138 entry for the cycle-as-a-whole. This entry shows who called the
139 cycle (as parents) and the members of the cycle (as children.)
141 were internal to the cycle, and the calls entry for each member shows,
143 the cycle.
Dprofile3.txt97 cycle, the cycle number is printed between the
116 member of a cycle, the cycle number is printed between
138 member of a cycle, the cycle number is printed
142 entry for the cycle-as-a-whole. This entry shows who called the
143 cycle (as parents) and the members of the cycle (as children.)
145 were internal to the cycle, and the calls entry for each member shows,
147 the cycle.
/third_party/uboot/u-boot-2020.01/drivers/pwm/
DKconfig6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
31 programmable period and duty cycle. A 32-bit counter is used.
48 four channels with a programmable period and duty cycle. Only a
49 32KHz clock is supported by the driver but the duty cycle is
57 programmable period and duty cycle. A 16-bit counter is used.
/third_party/littlefs/scripts/
Dreadtree.py16 cycle = False
24 cycle = m.blocks
25 if cycle:
155 if cycle:
158 cycle[0], cycle[1]))
/third_party/uboot/u-boot-2020.01/board/buffalo/lsxl/
Dkwbimage-lschl.cfg38 # bit4: 0, addr/cmd in same cycle
55 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
56 # bit7-4: 4, 5 cycle tRCD
60 # bit20: 0, 16 cycle tRAS (tRAS[4])
62 # bit27-24: 3, 4 cycle tRRD
67 # bit6-0: 0x23, 35 cycle tRFC
68 # bit8-7: 0, 1 cycle tR2R
130 # bit9: 0, no half clock cycle addition to dataout
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
Dkwbimage-lsxhl.cfg55 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
56 # bit7-4: 4, 5 cycle tRCD
60 # bit20: 1, 18 cycle tRAS (tRAS[4])
62 # bit27-24: 2, 3 cycle tRRD
67 # bit6-0: 0x32, 50 cycle tRFC
68 # bit8-7: 0, 1 cycle tR2R
130 # bit9: 0, no half clock cycle addition to dataout
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
/third_party/gstreamer/gstplugins_good/gst/goom2k1/
Dgoom_core.c38 goomdata->cycle = 0; in goom_init()
215 if ((pzfd->reverse) && (!(goomdata->cycle % 12)) && (rand () % 3 == 0)) { in goom_update()
309 (goomdata->cycle % 3 == 0)) || (iRAND (goomdata, 40) == 0)) { in goom_update()
335 && (goomdata->cycle % 16 == 0)) { in goom_update()
350 if ((goomdata->cycle % 73 == 0) && (pzfd->vitesse < STOP_SPEED - 5)) { in goom_update()
359 if ((goomdata->cycle % 101 == 0) && (pzfd->pertedec == 7)) { in goom_update()
381 goomdata->cycle++; in goom_update()
385 if (!(goomdata->cycle % 100)) { in goom_update()
/third_party/uboot/u-boot-2020.01/board/d-link/dns325/
Dkwbimage.cfg36 # bit4: 0, addr/cmd in smame cycle
52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
53 # bit7-4: 5, 6 cycle tRCD
57 # bit20: 1, 18 cycle tRAS (tRAS[4])
59 # bit27-24: 2, 3 cycle tRRD
63 # bit6-0: 0x33, 33 cycle tRFC
64 # bit8-7: 0, 1 cycle tR2R
120 # bit9: 0, no half clock cycle addition to dataout
121 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td46 // Each LSU pipeline can complete a load or store in one cycle.
51 // FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
52 // VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
54 // Frequent FX ops. take only one cycle and results can be used again in the
55 // next cycle (there is a self-bypass). Getting results from the other FX
56 // pipeline takes an additional cycle.
61 // (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
69 // share the same write-back, and have a 5-cycle latency difference, so the
387 let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
390 // cycle (from all queues) is 8.
/third_party/boost/boost/hana/fwd/
Dcycle.hpp60 constexpr auto cycle = [](auto&& xs, auto const& n) { in __anona78855500102() variable
72 constexpr cycle_t cycle{};

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