Searched refs:ddr_sr_cntr (Results 1 – 14 of 14) sorted by relevance
| /third_party/uboot/u-boot-2020.01/board/freescale/bsc9132qds/ |
| D | ddr.c | 40 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
67 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
|
| /third_party/uboot/u-boot-2020.01/board/freescale/p1010rdb/ |
| D | ddr.c | 43 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
70 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
|
| /third_party/uboot/u-boot-2020.01/board/freescale/p1_twr/ |
| D | ddr.c | 49 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/ls1043ardb/ |
| D | ddr.h | 97 .ddr_sr_cntr = 0,
|
| /third_party/uboot/u-boot-2020.01/drivers/ddr/fsl/ |
| D | arm_ddr_gen3.c | 123 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
|
| D | mpc85xx_ddr_gen3.c | 146 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
|
| D | fsl_ddr_gen4.c | 209 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
|
| D | interactive.c | 671 CFG_REGS(ddr_sr_cntr), in print_fsl_memctl_config_regs()
762 CFG_REGS(ddr_sr_cntr), in fsl_ddr_regs_edit()
|
| D | ctrl_regs.c | 2304 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
|
| /third_party/uboot/u-boot-2020.01/board/Arcturus/ucp1020/ |
| D | ddr.c | 109 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/bsc9131rdb/ |
| D | ddr.c | 41 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
|
| /third_party/uboot/u-boot-2020.01/board/freescale/p1_p2_rdb_pc/ |
| D | ddr.c | 241 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/include/ |
| D | fsl_immap.h | 57 u32 ddr_sr_cntr; /* self refresh counter */ member
|
| D | fsl_ddr_sdram.h | 287 unsigned int ddr_sr_cntr; member
|