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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsHexagon.td71 def int_hexagon_circ_ldd :
76 def int_hexagon_circ_ldw :
81 def int_hexagon_circ_ldh :
86 def int_hexagon_circ_lduh :
91 def int_hexagon_circ_ldb :
96 def int_hexagon_circ_ldub :
102 def int_hexagon_circ_std :
107 def int_hexagon_circ_stw :
112 def int_hexagon_circ_sth :
117 def int_hexagon_circ_sthhi :
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DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
21 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
24 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
27 def int_aarch64_clrex : Intrinsic<[]>;
29 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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DIntrinsicsPowerPC.td20 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
21 def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
24 def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
25 def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
27 def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
29 def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
30 def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
33 def int_ppc_sync : Intrinsic<[], [], []>;
35 def int_ppc_lwsync : Intrinsic<[], [], []>;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSystemOperands.td36 def SysRegsList : GenericTable {
45 def lookupSysRegByName : SearchIndex {
57 def : SysReg<"ustatus", 0x000>;
58 def : SysReg<"uie", 0x004>;
59 def : SysReg<"utvec", 0x005>;
64 def : SysReg<"uscratch", 0x040>;
65 def : SysReg<"uepc", 0x041>;
66 def : SysReg<"ucause", 0x042>;
67 def : SysReg<"utval", 0x043>;
68 def : SysReg<"uip", 0x044>;
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DRISCVSchedRocket64.td14 def Rocket64Model : SchedMachineModel {
28 def Rocket64UnitALU : ProcResource<1>; // Int ALU
29 def Rocket64UnitIMul : ProcResource<1>; // Int Multiply
30 def Rocket64UnitMem : ProcResource<1>; // Load/Store
31 def Rocket64UnitB : ProcResource<1>; // Branch
33 def Rocket64UnitFPALU : ProcResource<1>; // FP ALU
37 def Rocket64UnitIDiv : ProcResource<1>; // Int Division
38 def Rocket64UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
47 def : WriteRes<WriteJmp, [Rocket64UnitB]>;
48 def : WriteRes<WriteJal, [Rocket64UnitB]>;
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DRISCVSchedRocket32.td14 def Rocket32Model : SchedMachineModel {
29 def Rocket32UnitALU : ProcResource<1>; // Int ALU
30 def Rocket32UnitIMul : ProcResource<1>; // Int Multiply
31 def Rocket32UnitMem : ProcResource<1>; // Load/Store
32 def Rocket32UnitB : ProcResource<1>; // Branch
34 def Rocket32UnitFPALU : ProcResource<1>; // FP ALU
38 def Rocket32UnitIDiv : ProcResource<1>; // Int Division
39 def Rocket32UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt'
48 def : WriteRes<WriteJmp, [Rocket32UnitB]>;
49 def : WriteRes<WriteJal, [Rocket32UnitB]>;
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DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations
14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
17 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
18 def WriteJmp : SchedWrite; // Jump
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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DHexagonDepITypes.td12 def TypeALU32_2op : IType<0>;
13 def TypeALU32_3op : IType<1>;
14 def TypeALU32_ADDI : IType<2>;
15 def TypeALU64 : IType<3>;
16 def TypeCJ : IType<4>;
17 def TypeCOPROC_VX : IType<5>;
18 def TypeCR : IType<6>;
19 def TypeCVI_4SLOT_MPY : IType<7>;
20 def TypeCVI_GATHER : IType<8>;
21 def TypeCVI_GATHER_RST : IType<9>;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
30 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
50 def Gfx9BufferFormat : GcnBufferFormatTable {
54 def Gfx10PlusBufferFormat : GcnBufferFormatTable {
59 def getGfx9BufferFormatInfo : SearchIndex {
63 def getGfx10PlusBufferFormatInfo : SearchIndex {
69 def : Gfx9BufferFormat< /*FORMAT_8_UNORM*/ 0x01, 8, 1, /*NUM_FORMAT_UNORM*/ 0, /*DA…
70 def : Gfx9BufferFormat< /*FORMAT_8_SNORM*/ 0x11, 8, 1, /*NUM_FORMAT_SNORM*/ 1, /*DA…
71 def : Gfx9BufferFormat< /*FORMAT_8_USCALED*/ 0x21, 8, 1, /*NUM_FORMAT_USCALED*/ 2, /*DA…
72 def : Gfx9BufferFormat< /*FORMAT_8_SSCALED*/ 0x31, 8, 1, /*NUM_FORMAT_SSCALED*/ 3, /*DA…
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRDevices.td35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
45 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
51 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
56 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
61 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
66 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
71 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
75 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
80 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td24 def sub_even : SubRegIndex<32>;
25 def sub_odd : SubRegIndex<32, 32>;
26 def sub_even64 : SubRegIndex<64>;
27 def sub_odd64 : SubRegIndex<64, 64>;
58 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
60 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
62 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
64 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
68 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSchedule.td12 def ALU : FuncUnit;
13 def IMULDIV : FuncUnit;
19 def IIM16Alu : InstrItinClass;
20 def IIPseudo : InstrItinClass;
22 def II_ABS : InstrItinClass;
23 def II_ADDI : InstrItinClass;
24 def II_ADDIU : InstrItinClass;
25 def II_ADDIUPC : InstrItinClass;
26 def II_ADD : InstrItinClass;
27 def II_ADDU : InstrItinClass;
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DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
42 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
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/third_party/boost/libs/coroutine/doc/
Dcoro.qbk23 [def __boost_asio__ [*Boost.Asio]]
24 [def __boost_build__ [*Boost.Build]]
25 [def __boost_context__ [*Boost.Context]]
26 [def __boost_coroutine__ [*Boost.Coroutine]]
27 [def __boost_exception__ [*Boost.Exception]]
28 [def __boost_function_types__ [*Boost.FunctionTypes]]
29 [def __boost_move__ [*Boost.Move]]
30 [def __boost_mpl__ [*Boost.MPL]]
31 [def __boost_optional__ [*Boost.Optional]]
32 [def __boost_preprocessor__ [*Boost.Preprocessor]]
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/third_party/boost/libs/python/test/
Dbuiltin_converters.cpp44 using boost::python::def;
66 def("get_type", get_type); in BOOST_PYTHON_MODULE()
67 def("return_null_handle", return_null_handle); in BOOST_PYTHON_MODULE()
70 def("bool_size", by_value<bool>::size); in BOOST_PYTHON_MODULE()
71 def("char_size", by_value<char>::size); in BOOST_PYTHON_MODULE()
72 def("int_size", by_value<int>::size); in BOOST_PYTHON_MODULE()
73 def("short_size", by_value<short>::size); in BOOST_PYTHON_MODULE()
74 def("long_size", by_value<long>::size); in BOOST_PYTHON_MODULE()
76 def("long_long_size", by_value<BOOST_PYTHON_LONG_LONG>::size); in BOOST_PYTHON_MODULE()
79 def("rewrap_value_bool", by_value<bool>::rewrap); in BOOST_PYTHON_MODULE()
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/third_party/boost/libs/icl/doc/
Dicl.qbk23 [def __itv__ [classref boost::icl::interval interval]]
24 [def __Itv__ [classref boost::icl::interval Interval]]
26 [def __itv_tr__ [classref boost::icl::interval_traits interval_traits]]
27 [def __Itv_tr__ [classref boost::icl::interval_traits Interval_traits]]
29 [def __ro_itv__ [classref boost::icl::right_open_interval right_open_interval]]
30 [def __lo_itv__ [classref boost::icl::left_open_interval left_open_interval]]
31 [def __op_itv__ [classref boost::icl::open_interval open_interval]]
32 [def __cl_itv__ [classref boost::icl::closed_interval closed_interval]]
34 [def __dc_itv__ [classref boost::icl::discrete_interval discrete_interval]]
35 [def __ct_itv__ [classref boost::icl::continuous_interval continuous_interval]]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedExynosM4.td19 def ExynosM4Model : SchedMachineModel {
35 def M4UnitA : ProcResource<2>; // Simple integer
36 def M4UnitC : ProcResource<2>; // Simple and complex integer
38 def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 def M4UnitE : ProcResource<1>; // CRC (inside C0)
41 def M4UnitB : ProcResource<2>; // Branch
42 def M4UnitL0 : ProcResource<1>; // Load
43 def M4UnitS0 : ProcResource<1>; // Store
44 def M4PipeLS : ProcResource<1>; // Load/Store
46 def M4UnitL1 : ProcResource<1>;
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DAArch64SchedExynosM3.td19 def ExynosM3Model : SchedMachineModel {
36 def M3UnitA : ProcResource<2>; // Simple integer
37 def M3UnitC : ProcResource<2>; // Simple and complex integer
38 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
39 def M3UnitB : ProcResource<2>; // Branch
40 def M3UnitL : ProcResource<2>; // Load
41 def M3UnitS : ProcResource<1>; // Store
42 def M3PipeF0 : ProcResource<1>; // FP #0
44 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
45 def M3UnitFADD0 : ProcResource<1>; // Simple FP
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DAArch64SystemOperands.td20 def HasCCPP : Predicate<"Subtarget->hasCCPP()">,
23 def HasPAN : Predicate<"Subtarget->hasPAN()">,
27 def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">,
31 def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,
53 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
54 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
55 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
56 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
57 def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;
58 def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>;
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DAArch64SchedExynosM5.td19 def ExynosM5Model : SchedMachineModel {
35 def M5UnitA : ProcResource<2>; // Simple integer
36 def M5UnitC : ProcResource<2>; // Simple and complex integer
38 def M5UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
39 def M5UnitE : ProcResource<2>; // Simple 32-bit integer
41 def M5UnitF : ProcResource<2>; // CRC (inside C)
42 def M5UnitB : ProcResource<1>; // Branch
43 def M5UnitL0 : ProcResource<1>; // Load
44 def M5UnitS0 : ProcResource<1>; // Store
45 def M5PipeLS : ProcResource<1>; // Load/Store
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DAArch64RegisterInfo.td22 def sub_32 : SubRegIndex<32>;
24 def bsub : SubRegIndex<8>;
25 def hsub : SubRegIndex<16>;
26 def ssub : SubRegIndex<32>;
27 def dsub : SubRegIndex<32>;
28 def sube32 : SubRegIndex<32>;
29 def subo32 : SubRegIndex<32>;
30 def qhisub : SubRegIndex<64>;
31 def qsub : SubRegIndex<64>;
32 def sube64 : SubRegIndex<64>;
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/third_party/boost/libs/coroutine2/doc/
Dcoro.qbk23 [def __boost_asio__ [*Boost.Asio]]
24 [def __boost_build__ [*Boost.Build]]
25 [def __boost_context__ [*Boost.Context]]
26 [def __boost_coroutine__ [*Boost.Coroutine2]]
28 [def __coro__ ['coroutine]]
29 [def __coro_fn__ ['coroutine-function]]
30 [def __coros__ ['coroutines]]
31 [def __ctx__ ['context]]
32 [def __not_a_coro__ ['not-a-coroutine]]
33 [def __segmented_stack__ ['segmented-stack]]
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