Searched refs:div_cfg (Results 1 – 3 of 3) sorted by relevance
270 struct ast2500_div_config div_cfg = { in ast2500_configure_ddr() local276 ast2500_calc_clock_config(clkin, rate, &div_cfg); in ast2500_configure_ddr()281 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) in ast2500_configure_ddr()282 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) in ast2500_configure_ddr()283 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); in ast2500_configure_ddr()379 struct ast2500_div_config div_cfg = { in ast2500_configure_d2pll() local399 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); in ast2500_configure_d2pll()402 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) in ast2500_configure_d2pll()403 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) in ast2500_configure_d2pll()404 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), in ast2500_configure_d2pll()
1300 phy_div_cfg *div_cfg = HI_NULL; in phy_div_cfg_get() local1302 for (div_cfg = &g_phy_div_cfg_tab[0]; in phy_div_cfg_get()1303 (div_cfg != HI_NULL && (i < HDMI_ARRAY_SIZE(g_phy_div_cfg_tab))); in phy_div_cfg_get()1304 div_cfg++, i++) { in phy_div_cfg_get()1305 … if ((pix_clk >= div_cfg->pix_clk_range.clk_min) && (pix_clk <= div_cfg->pix_clk_range.clk_max) && in phy_div_cfg_get()1306 (deep_clr == div_cfg->deep_color)) { in phy_div_cfg_get()1307 return div_cfg; in phy_div_cfg_get()1726 phy_div_cfg *div_cfg = HI_NULL; in hal_hdmi_phy_tmds_set() local1741 div_cfg = phy_div_cfg_get(hdmi_tmds_cfg->pixel_clk, dp_color); in hal_hdmi_phy_tmds_set()1742 hdmi_if_null_return(div_cfg, HI_FAILURE); in hal_hdmi_phy_tmds_set()[all …]
20 u32 div_cfg; member