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/third_party/uboot/u-boot-2020.01/drivers/clk/
Dclk-divider.c73 struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ? in clk_divider_recalc_rate() local
79 val = divider->io_divider_val; in clk_divider_recalc_rate()
81 val = readl(divider->reg); in clk_divider_recalc_rate()
83 val >>= divider->shift; in clk_divider_recalc_rate()
84 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
86 return divider_recalc_rate(clk, parent_rate, val, divider->table, in clk_divider_recalc_rate()
87 divider->flags, divider->width); in clk_divider_recalc_rate()
153 struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ? in clk_divider_set_rate() local
159 value = divider_get_val(rate, parent_rate, divider->table, in clk_divider_set_rate()
160 divider->width, divider->flags); in clk_divider_set_rate()
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Dclk_sandbox_ccf.c147 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); in sandbox_clk_composite_divider_recalc_rate() local
152 val = divider->io_divider_val; in sandbox_clk_composite_divider_recalc_rate()
153 val >>= divider->shift; in sandbox_clk_composite_divider_recalc_rate()
154 val &= clk_div_mask(divider->width); in sandbox_clk_composite_divider_recalc_rate()
156 return divider_recalc_rate(clk, parent_rate, val, divider->table, in sandbox_clk_composite_divider_recalc_rate()
157 divider->flags, divider->width); in sandbox_clk_composite_divider_recalc_rate()
Dclk_stm32h7.c430 u32 divider; in stm32_get_HSI_divider() local
433 divider = readl(&regs->cr) & RCC_CR_HSIDIV_MASK; in stm32_get_HSI_divider()
434 divider = divider >> RCC_CR_HSIDIV_SHIFT; in stm32_get_HSI_divider()
436 return divider; in stm32_get_HSI_divider()
462 u32 divider; in stm32_get_rate() local
481 divider = 0; in stm32_get_rate()
483 divider = stm32_get_HSI_divider(regs); in stm32_get_rate()
486 divider, clk_get_rate(&clk)); in stm32_get_rate()
488 return clk_get_rate(&clk) >> divider; in stm32_get_rate()
/third_party/uboot/u-boot-2020.01/drivers/clk/imx/
Dclk-composite-8m.c32 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); in imx8m_clk_composite_divider_recalc_rate() local
40 (&composite->clk)->dev->name, parent_rate, divider->reg); in imx8m_clk_composite_divider_recalc_rate()
41 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
42 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
45 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
46 divider->width); in imx8m_clk_composite_divider_recalc_rate()
48 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
52 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
88 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); in imx8m_clk_composite_divider_set_rate() local
101 val = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
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/third_party/uboot/u-boot-2020.01/arch/x86/lib/
Ddiv64.c57 static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p) in _64bit_divide() argument
65 if (!divider) in _64bit_divide()
66 return 1 / (u32)divider; in _64bit_divide()
70 if (divider > MAX_32BIT_UINT) { in _64bit_divide()
73 *rem_p = divider; in _64bit_divide()
75 result = (u32)dividend / (u32)divider; in _64bit_divide()
77 *rem_p = (u32)dividend % (u32)divider; in _64bit_divide()
82 while (divider <= dividend) { in _64bit_divide()
83 u64 locald = divider; in _64bit_divide()
/third_party/flutter/flutter/packages/flutter/lib/src/material/
Ddivider.dart16 /// In the material design language, this represents a divider. Dividers can be
19 /// To create a divider between [ListTile] items, consider using
31 /// Creates a material design divider.
49 /// The divider's height extent.
51 /// The divider itself is always drawn as a horizontal line that is centered
58 /// The thickness of the line drawn within the divider.
60 /// A divider with a [thickness] of 0.0 is always drawn as a line with a
67 /// The amount of empty space to the leading edge of the divider.
73 /// The amount of empty space to the trailing edge of the divider.
94 /// Computes the [BorderSide] that represents a divider of the specified
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/third_party/uboot/u-boot-2020.01/arch/arm/dts/
Ddm816x-clocks.dtsi99 compatible = "ti,divider-clock";
117 compatible = "ti,divider-clock";
125 compatible = "ti,divider-clock";
133 compatible = "ti,divider-clock";
141 compatible = "ti,divider-clock";
149 compatible = "ti,divider-clock";
157 compatible = "ti,divider-clock";
165 compatible = "ti,divider-clock";
173 compatible = "ti,divider-clock";
189 compatible = "ti,divider-clock";
Ddra7xx-clocks.dtsi214 compatible = "ti,divider-clock";
225 compatible = "ti,divider-clock";
234 compatible = "ti,divider-clock";
245 compatible = "ti,divider-clock";
277 compatible = "ti,divider-clock";
303 compatible = "ti,divider-clock";
347 compatible = "ti,divider-clock";
385 compatible = "ti,divider-clock";
423 compatible = "ti,divider-clock";
436 compatible = "ti,divider-clock";
[all …]
Dam43xx-clocks.dtsi213 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
235 compatible = "ti,divider-clock";
253 compatible = "ti,divider-clock";
271 compatible = "ti,divider-clock";
289 compatible = "ti,divider-clock";
308 compatible = "ti,divider-clock";
568 compatible = "ti,divider-clock";
591 compatible = "ti,divider-clock";
667 compatible = "ti,divider-clock";
[all …]
Dam33xx-clocks.dtsi181 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
199 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
255 compatible = "ti,divider-clock";
272 compatible = "ti,divider-clock";
510 compatible = "ti,divider-clock";
525 compatible = "ti,divider-clock";
Dimx6qdl-dhcom.dtsi138 lltc,fb-voltage-divider = <100000 110000>;
148 lltc,fb-voltage-divider = <100000 28000>;
157 lltc,fb-voltage-divider = <100000 110000>;
167 lltc,fb-voltage-divider = <100000 93100>;
176 lltc,fb-voltage-divider = <102000 29400>;
184 lltc,fb-voltage-divider = <100000 41200>;
/third_party/uboot/u-boot-2020.01/arch/arm/mach-tegra/
Dclock.c249 u64 divider = parent_rate * 2; in clk_get_divider() local
252 divider += rate - 1; in clk_get_divider()
253 do_div(divider, rate); in clk_get_divider()
255 if ((s64)divider - 2 < 0) in clk_get_divider()
258 if ((s64)divider - 2 >= max_divider) in clk_get_divider()
261 return divider - 2; in clk_get_divider()
301 int divider) in get_rate_from_divider() argument
306 do_div(rate, divider + 2); in get_rate_from_divider()
379 int divider = clk_get_divider(divider_bits, divided_parent, in find_best_divider() local
382 divider); in find_best_divider()
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/third_party/freetype/src/psaux/
Dpsconv.c204 FT_Long divider = 1; in PS_Conv_ToFixed() local
261 if ( divider < 0xCCCCCCCL && decimal < 0xCCCCCCCL ) in PS_Conv_ToFixed()
268 divider *= 10; in PS_Conv_ToFixed()
314 if ( divider == 1 ) in PS_Conv_ToFixed()
316 divider /= 10; in PS_Conv_ToFixed()
327 if ( divider < 0xCCCCCCCL ) in PS_Conv_ToFixed()
328 divider *= 10; in PS_Conv_ToFixed()
340 decimal = FT_DivFix( decimal, divider ); in PS_Conv_ToFixed()
/third_party/skia/third_party/externals/freetype/src/psaux/
Dpsconv.c204 FT_Long divider = 1; in PS_Conv_ToFixed() local
261 if ( divider < 0xCCCCCCCL && decimal < 0xCCCCCCCL ) in PS_Conv_ToFixed()
268 divider *= 10; in PS_Conv_ToFixed()
314 if ( divider == 1 ) in PS_Conv_ToFixed()
316 divider /= 10; in PS_Conv_ToFixed()
327 if ( divider < 0xCCCCCCCL ) in PS_Conv_ToFixed()
328 divider *= 10; in PS_Conv_ToFixed()
340 decimal = FT_DivFix( decimal, divider ); in PS_Conv_ToFixed()
/third_party/flutter/skia/third_party/externals/freetype/src/psaux/
Dpsconv.c205 FT_Long divider = 1; in PS_Conv_ToFixed() local
262 if ( divider < 0xCCCCCCCL && decimal < 0xCCCCCCCL ) in PS_Conv_ToFixed()
269 divider *= 10; in PS_Conv_ToFixed()
315 if ( divider == 1 ) in PS_Conv_ToFixed()
317 divider /= 10; in PS_Conv_ToFixed()
328 if ( divider < 0xCCCCCCCL ) in PS_Conv_ToFixed()
329 divider *= 10; in PS_Conv_ToFixed()
341 decimal = FT_DivFix( decimal, divider ); in PS_Conv_ToFixed()
/third_party/node/lib/internal/
Dcli_table.js69 const divider = columnWidths.map((i) => constant
72 let result = `${tableChars.topLeft}${divider.join(tableChars.topMiddle)}` +
74 `${tableChars.leftMiddle}${divider.join(tableChars.rowMiddle)}` +
80 result += `${tableChars.bottomLeft}${divider.join(tableChars.bottomMiddle)}` +
/third_party/uboot/u-boot-2020.01/arch/m68k/cpu/mcf532x/
Dspeed.c54 int divider; in get_sys_clock() local
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
60 return (FREF / (3 * (1 << divider))); in get_sys_clock()
63 return (FREF / (2 << divider)); in get_sys_clock()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/fsl-layerscape/
DKconfig462 int "Platform clock divider"
469 This is the divider that is used to derive Platform clock from
474 int "DSPI clock divider"
478 This is the divider that is used to derive DSPI clock from Platform
482 int "DUART clock divider"
487 This is the divider that is used to derive DUART clock from Platform
491 int "I2C clock divider"
499 This is the divider that is used to derive I2C clock from Platform
503 int "IFC clock divider"
511 This is the divider that is used to derive IFC clock from Platform
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/third_party/uboot/u-boot-2020.01/arch/powerpc/cpu/mpc8xx/
Dspeed.c21 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); in get_clocks() local
39 gd->arch.brg_clk = gd->cpu_clk / divider; in get_clocks()
/third_party/uboot/u-boot-2020.01/drivers/i2c/
Dfsl_i2c.c86 unsigned short divider; member
123 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); in set_i2c_bus_speed() local
145 speed = i2c_clk / divider; /* Fake something */ in set_i2c_bus_speed()
156 if (c_div > divider && c_div < est_div) { in set_i2c_bus_speed()
181 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); in set_i2c_bus_speed()
190 if (fsl_i2c_speed_map[i].divider >= divider) { in set_i2c_bus_speed()
194 speed = i2c_clk / fsl_i2c_speed_map[i].divider; in set_i2c_bus_speed()
/third_party/uboot/u-boot-2020.01/drivers/mmc/
Dmxcmmc.c424 unsigned int divider; in mxcmci_set_clk_rate() local
429 for (divider = 1; divider <= 0xF; divider++) { in mxcmci_set_clk_rate()
432 x = (clk_in / (divider + 1)); in mxcmci_set_clk_rate()
440 if (divider < 0x10) in mxcmci_set_clk_rate()
449 writel((prescaler << 4) | divider, &host->base->clk_rate); in mxcmci_set_clk_rate()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/arm926ejs/mxs/
Dspl_mem_init.c147 const unsigned char divider = 33; in mxs_mem_init_clock() local
150 const unsigned char divider = 21; in mxs_mem_init_clock() local
160 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), in mxs_mem_init_clock()
/third_party/uboot/u-boot-2020.01/drivers/serial/
Dserial_pxa.c61 uint32_t divider = pxa_uart_get_baud_divider(baudrate); in pxa_setbrg_common() local
62 if (!divider) in pxa_setbrg_common()
74 writel(divider & 0xff, &uart_regs->dll); in pxa_setbrg_common()
75 writel(divider >> 8, &uart_regs->dlh); in pxa_setbrg_common()
Dserial_bcm283x_mu.c60 u32 divider; in bcm283x_mu_serial_setbrg() local
65 divider = plat->clock / (baudrate * 8); in bcm283x_mu_serial_setbrg()
68 writel(divider - 1, &regs->baud); in bcm283x_mu_serial_setbrg()
/third_party/ltp/lib/
Drandom_range.c99 static long long divider(long long, long long, long long, long long);
352 randnum = divider(min, max, 0, -1); in random_range()
439 randnum = divider(min, max, 0, -1); in random_rangel()
526 randnum = divider(min, max, 0, -1); in random_rangell()
547 divider(long long min, long long max, long long cnt, long long rand) in divider() function
596 return divider(med, max, cnt + 1, rand); in divider()
598 return divider(min, med, cnt + 1, rand); in divider()

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