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Searched refs:epll_con (Results 1 – 3 of 3) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/mach-s5pc1xx/include/mach/
Dclock.h20 unsigned int epll_con; member
55 unsigned int epll_con; member
/third_party/uboot/u-boot-2020.01/arch/arm/mach-s5pc1xx/
Dclock.c40 r = readl(&clk->epll_con); in s5pc100_get_pll_clk()
91 r = readl(&clk->epll_con); in s5pc110_get_pll_clk()
/third_party/uboot/u-boot-2020.01/arch/arm/mach-exynos/
Dclock.c1268 unsigned int epll_con, epll_con_k; in exynos5_set_epll_clk() local
1275 epll_con = readl(&clk->epll_con0); in exynos5_set_epll_clk()
1276 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << in exynos5_set_epll_clk()
1291 epll_con |= exynos5_epll_div[i].en_lock_det << in exynos5_set_epll_clk()
1293 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; in exynos5_set_epll_clk()
1294 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; in exynos5_set_epll_clk()
1295 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; in exynos5_set_epll_clk()
1305 writel(epll_con, &clk->epll_con0); in exynos5_set_epll_clk()