Searched refs:fmc_cmd_cmd1 (Results 1 – 14 of 14) sorted by relevance
125 reg = fmc_cmd_cmd1(SPI_CMD_WREN); in spi_general_write_enable()186 hifmc_write(host, FMC_CMD, fmc_cmd_cmd1(reg)); in spi_general_entry_4addr()247 reg = fmc_cmd_cmd1(SPI_CMD_WRSR); in spi_general_set_cmd()366 regval = fmc_cmd_cmd1(SPI_CMD_WRSR3); in spi_nor_reset_pin_enable()
38 regval = fmc_cmd_cmd1(cmd); in spi_w25q256fv_set_cmd()111 regval = fmc_cmd_cmd1(SPI_CMD_WRSR2); in spi_w25q256fv_set_op()
65 regval = fmc_cmd_cmd1(SPI_CMD_WRSR); in spi_mx25l25635e_set_cmd()145 regval = fmc_cmd_cmd1(SPI_CMD_WRSR); in spi_mxic_set_reg()
68 hifmc_write(host, FMC_CMD, fmc_cmd_cmd1(reg)); in spi_micron_entry_4addr()
67 regval = fmc_cmd_cmd1(SPI_CMD_WRSR2); in spi_puya_qe_enable()
34 reg = fmc_cmd_cmd1(SPI_CMD_WRSR); in spi_issi_set_cmd()
43 regval = fmc_cmd_cmd1(SS_SPI_CMD_BRWR); in spi_s25fl256s_set_cmd()
33 regval = fmc_cmd_cmd1(SPI_CMD_WRSR); in spi_xtx_set_op()
348 reg = fmc_cmd_cmd1(SPI_CMD_RDID); in hifmc100_read_ids()393 regval = fmc_cmd_cmd1(spi->erase->cmd); in hifmc100_reg_erase_one_block()494 hifmc_write(host, FMC_CMD, fmc_cmd_cmd1(spi->write->cmd)); in hifmc100_reg_write_buf()1073 reg = fmc_cmd_cmd1(SPI_CMD_WRSR); in hifmc100_set_bp_val()1420 regval = fmc_cmd_cmd1(opcode); in hifmc100_op_reg()
35 regval = fmc_cmd_cmd1(cmd); in set_cmd()
32 reg = fmc_cmd_cmd1(op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES); in spi_nand_set_cmd()173 reg = fmc_cmd_cmd1(SPI_CMD_WREN); in spi_general_write_enable()
331 hifmc_write(host, FMC_CMD, fmc_cmd_cmd1(reg)); in hifmc100_send_cmd_erase()400 reg = fmc_cmd_cmd1(SPI_CMD_RDID); in hifmc100_send_cmd_readid()438 reg = fmc_cmd_cmd1(SPI_CMD_RESET); in hifmc100_send_cmd_reset()
126 reg = fmc_cmd_cmd2(NAND_CMD_PAGEPROG) | fmc_cmd_cmd1(NAND_CMD_SEQIN); in hifmc100_send_cmd_write()176 reg = fmc_cmd_cmd2(NAND_CMD_READSTART) | fmc_cmd_cmd1(NAND_CMD_READ0); in hifmc100_send_cmd_read()215 reg = fmc_cmd_cmd2(NAND_CMD_ERASE2) | fmc_cmd_cmd1(NAND_CMD_ERASE1); in hifmc100_send_cmd_erase()311 reg = fmc_cmd_cmd1(NAND_CMD_READID); in hifmc100_send_cmd_readid()345 reg = fmc_cmd_cmd1(NAND_CMD_RESET); in hifmc100_send_cmd_reset()
225 #define fmc_cmd_cmd1(_cmd) ((_cmd) & 0xff) macro