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Searched refs:fmc_pr (Results 1 – 25 of 33) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/mtd/spi/hifmc100/
Dhifmc100_spi_general.c35 fmc_pr(SR_DBG, "\t * Start get flash Register[%#x]\n", cmd); in spi_general_get_flash_register()
46 fmc_pr(SR_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, cmd); in spi_general_get_flash_register()
50 fmc_pr(SR_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg); in spi_general_get_flash_register()
57 fmc_pr(SR_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, reg); in spi_general_get_flash_register()
65 fmc_pr(SR_DBG, "\t * End get flash Register[%#x], val: %#x\n", cmd, in spi_general_get_flash_register()
106 fmc_pr(WE_DBG, "\t * Start Write Enable\n"); in spi_general_write_enable()
109 fmc_pr(WE_DBG, "\t Read Status Register[%#x]:%#x\n", SPI_CMD_RDSR, in spi_general_write_enable()
112 fmc_pr(WE_DBG, "\t Write Enable was opened! reg: %#x\n", in spi_general_write_enable()
121 fmc_pr(WE_DBG, "\t Set GLOBAL_CFG[%#x]%#x\n", in spi_general_write_enable()
127 fmc_pr(WE_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, reg); in spi_general_write_enable()
[all …]
Dhifmc100_spi_w25q256fv.c40 fmc_pr(AC_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval); in spi_w25q256fv_set_cmd()
44 fmc_pr(AC_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in spi_w25q256fv_set_cmd()
48 fmc_pr(AC_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval); in spi_w25q256fv_set_cmd()
58 fmc_pr(AC_DBG, "\t* Start W25Q256FV SPI Nor %s 4-byte mode.\n", in spi_w25q256fv_entry_4addr()
62 fmc_pr(AC_DBG, "\t* W25Q(128/256)FV not support 4B mode.\n"); in spi_w25q256fv_entry_4addr()
67 fmc_pr(AC_DBG, "\t Read Status Register-3[%#x]:%#x\n", SPI_CMD_RDSR3, in spi_w25q256fv_entry_4addr()
70 fmc_pr(AC_DBG, "\t* 4-byte was %sd, reg:%#x\n", str[enable], in spi_w25q256fv_entry_4addr()
81 fmc_pr(AC_DBG, "\t Get Status Register 3[%#x]:%#x\n", in spi_w25q256fv_entry_4addr()
84 fmc_pr(AC_DBG, "\t Enter 4-byte success, reg[%#x]\n", in spi_w25q256fv_entry_4addr()
95 fmc_pr(AC_DBG, "\tnow W25Q256FV start software reset\n"); in spi_w25q256fv_entry_4addr()
[all …]
Dhifmc100_spi_gd25qxxx.c37 fmc_pr(QE_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, regval); in set_cmd()
41 fmc_pr(QE_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in set_cmd()
45 fmc_pr(QE_DBG, "\t|-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval); in set_cmd()
51 fmc_pr(QE_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, regval); in set_cmd()
66 fmc_pr(QE_DBG, "\t|-Read GD SR-1[%#x], val: %#x\n", GD_SPI_CMD_RDSR1, in gd_16pin_qe_enable()
69 fmc_pr(QE_DBG, "\t* Quad was %sd, status:%#x\n", str[op], in gd_16pin_qe_enable()
75 fmc_pr(QE_DBG, "\t|-First, 16Pin GD flash %s Quad.\n", str[op]); in gd_16pin_qe_enable()
78 fmc_pr(QE_DBG, "\t|-Read Status Register[%#x]%#x\n", SPI_CMD_RDSR, in gd_16pin_qe_enable()
89 fmc_pr(QE_DBG, "\t|-Write IO[%p]%#x\n", host->iobase, in gd_16pin_qe_enable()
95 fmc_pr(QE_DBG, "\t|-Read GD SR-1[%#x], val: %#x\n", GD_SPI_CMD_RDSR1, in gd_16pin_qe_enable()
[all …]
Dhifmc100.c71 fmc_pr(DMA_DB, "\t\t *-Start dma transfer => [%#x], len[%#x], buf = %p\n", in hifmc100_dma_transfer()
76 fmc_pr(DMA_DB, "\t\t Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, regval); in hifmc100_dma_transfer()
80 fmc_pr(DMA_DB, "\t\t Set ADDRL[%#x]%#x\n", FMC_ADDRL, regval); in hifmc100_dma_transfer()
96 fmc_pr(DMA_DB, "\t\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in hifmc100_dma_transfer()
100 fmc_pr(DMA_DB, "\t\t Set DMA_LEN[%#x]%#x\n", FMC_DMA_LEN, regval); in hifmc100_dma_transfer()
104 fmc_pr(DMA_DB, "\t\t Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, in hifmc100_dma_transfer()
109 fmc_pr(DMA_DB, "\t\t Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, in hifmc100_dma_transfer()
116 fmc_pr(DMA_DB, "\t\t Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, regval); in hifmc100_dma_transfer()
120 fmc_pr(DMA_DB, "\t\t *-End dma transfer.\n"); in hifmc100_dma_transfer()
133 fmc_pr(DMA_DB, "* Start reg read, from:%#x len:%#x\n", spi_start_addr, in hifmc100_reg_read_buf()
[all …]
Dhifmc100_os.c61 fmc_pr(BT_DBG, "\t|*-Start SPI nor flash driver probe\n"); in hifmc100_driver_probe()
66 fmc_pr(BT_DBG, "\t|*-IP version unknown, result: %d\n", ret); in hifmc100_driver_probe()
70 fmc_pr(BT_DBG, "\t||-SPI nor host init\n"); in hifmc100_driver_probe()
74 fmc_pr(BT_DBG, "Error: SPI Nor init failed, ret: %d\n", ret); in hifmc100_driver_probe()
79 fmc_pr(BT_DBG, "\t|*-End SPI nor flash driver probe\n"); in hifmc100_driver_probe()
104 fmc_pr(BT_DBG, "\t|*-Start probe SPI nor flash total size\n"); in hifmc100_probe_spi_size()
106 fmc_pr(BT_DBG, "\t||-SPI nor flash[%d]: %dMB\n", ix, in hifmc100_probe_spi_size()
113 fmc_pr(BT_DBG, "\t|*-Probe SPI nor total size: %dMB, chip num: %d\n", in hifmc100_probe_spi_size()
122 fmc_pr(BT_DBG, "\t*-Start SPI Nor flash probe\n"); in hifmc100_spi_nor_probe()
125 fmc_pr(BT_DBG, "\t*-SPI Nor flash is initialized.\n"); in hifmc100_spi_nor_probe()
[all …]
Dhifmc100_spi_mx25l25635e.c67 fmc_pr(QE_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, regval); in spi_mx25l25635e_set_cmd()
71 fmc_pr(QE_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in spi_mx25l25635e_set_cmd()
75 fmc_pr(QE_DBG, "\t||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval); in spi_mx25l25635e_set_cmd()
80 fmc_pr(QE_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, regval); in spi_mx25l25635e_set_cmd()
95 fmc_pr(QE_DBG, "\t|*-Start MXIC SPI Nor %s Quad.\n", str[op]); in spi_mx25l25635e_qe_enable()
98 fmc_pr(QE_DBG, "\t||-Read Status Register[%#x]%#x\n", SPI_CMD_RDSR, in spi_mx25l25635e_qe_enable()
106 fmc_pr(QE_DBG, "\t|*-Quad was %sd, status:%#x\n", str[op], in spi_mx25l25635e_qe_enable()
119 fmc_pr(QE_DBG, "\t||-Write IO[%p]%#x\n", host->iobase, in spi_mx25l25635e_qe_enable()
128 fmc_pr(QE_DBG, "\t||-%s Quad success, status:%#x.\n", str[op], in spi_mx25l25635e_qe_enable()
133 fmc_pr(QE_DBG, "\t|*-End MXIC SPI Nor %s Quad.\n", str[op]); in spi_mx25l25635e_qe_enable()
[all …]
Dhifmc100_spi_s25fl256s.c45 fmc_pr(AC_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval); in spi_s25fl256s_set_cmd()
49 fmc_pr(AC_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in spi_s25fl256s_set_cmd()
53 fmc_pr(AC_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval); in spi_s25fl256s_set_cmd()
59 fmc_pr(AC_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval); in spi_s25fl256s_set_cmd()
73 fmc_pr(AC_DBG, "\t* Start SpanSion SPI Nor %s 4-byte mode.\n", in spi_s25fl256s_entry_4addr()
77 fmc_pr(AC_DBG, "\t* Flash isn't support 4-byte mode.\n"); in spi_s25fl256s_entry_4addr()
83 fmc_pr(AC_DBG, "\t Read Bank Register[%#x]%#x\n", SS_SPI_CMD_BRRD, in spi_s25fl256s_entry_4addr()
86 fmc_pr(AC_DBG, "\t* 4-byte was %sd, bank:%#x\n", str[enable], in spi_s25fl256s_entry_4addr()
97 fmc_pr(AC_DBG, "\t Write IO[%p]%#x\n", host->iobase, in spi_s25fl256s_entry_4addr()
106 fmc_pr(AC_DBG, "\t Read Bank Register[%#x]%#x\n", SS_SPI_CMD_BRRD, in spi_s25fl256s_entry_4addr()
[all …]
Dhifmc100_spi_micron.c45 fmc_pr(AC_DBG, "\t* Start SPI Nor %s 4-byte mode.\n", in spi_micron_entry_4addr()
49 fmc_pr(AC_DBG, "\t* Not support 4B mode.\n"); in spi_micron_entry_4addr()
54 fmc_pr(AC_DBG, "\t Read flag status register[%#x]:%#x\n", in spi_micron_entry_4addr()
57 fmc_pr(AC_DBG, "\t* 4-byte was %sd, reg:%#x\n", str[enable], in spi_micron_entry_4addr()
69 fmc_pr(AC_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, reg); in spi_micron_entry_4addr()
73 fmc_pr(AC_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg); in spi_micron_entry_4addr()
77 fmc_pr(AC_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, reg); in spi_micron_entry_4addr()
85 fmc_pr(AC_DBG, "\t Read flag status register[%#x]:%#x\n", in spi_micron_entry_4addr()
93 fmc_pr(AC_DBG, "\t %s 4-byte success, SR3:%#x\n", str[enable], status); in spi_micron_entry_4addr()
94 fmc_pr(AC_DBG, "\t* End SPI Nor flash %s 4-byte mode.\n", str[enable]); in spi_micron_entry_4addr()
Dhifmc100_spi_puya.c46 fmc_pr(QE_DBG, "\t* Start SPI Nor %s Quad.\n", str[op]); in spi_puya_qe_enable()
49 fmc_pr(QE_DBG, "\t Read Status Register-2[%#x]%#x\n", SPI_CMD_RDSR2, in spi_puya_qe_enable()
52 fmc_pr(QE_DBG, "\t* Quad was %s status:%#x\n", str[op], status); in spi_puya_qe_enable()
63 fmc_pr(QE_DBG, "\t Write IO[%#lx]%#x\n", (uintptr_t)host->iobase, in spi_puya_qe_enable()
69 fmc_pr(QE_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval); in spi_puya_qe_enable()
73 fmc_pr(QE_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in spi_puya_qe_enable()
77 fmc_pr(QE_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval); in spi_puya_qe_enable()
82 fmc_pr(QE_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval); in spi_puya_qe_enable()
90 fmc_pr(QE_DBG, "\t Read Status Register-2[%#x]:%#x\n", in spi_puya_qe_enable()
93 fmc_pr(QE_DBG, "\t %s Quad success. status:%#x\n", in spi_puya_qe_enable()
Dhifmc100_spi_issi.c36 fmc_pr(QE_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg); in spi_issi_set_cmd()
40 fmc_pr(QE_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg); in spi_issi_set_cmd()
44 fmc_pr(QE_DBG, "\t|-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg); in spi_issi_set_cmd()
50 fmc_pr(QE_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg); in spi_issi_set_cmd()
65 fmc_pr(QE_DBG, "\t*-Start SPI Nor %s Quad.\n", str[op]); in spi_issi_qe_enable()
68 fmc_pr(QE_DBG, "\t|-Read Config Register[%#x]%#x\n", SPI_CMD_RDSR, in spi_issi_qe_enable()
71 fmc_pr(QE_DBG, "\t* Quad was %sd, config:%#x\n", str[op], in spi_issi_qe_enable()
86 fmc_pr(QE_DBG, "\t|-Write IO[%p]%#x\n", host->iobase, in spi_issi_qe_enable()
95 fmc_pr(QE_DBG, "\t|-%s Quad success, config: %#x\n", str[op], in spi_issi_qe_enable()
101 fmc_pr(QE_DBG, "\t* End SPI Nor %s Quad.\n", str[op]); in spi_issi_qe_enable()
Dhifmc100_spi_xtx.c35 fmc_pr(QE_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval); in spi_xtx_set_op()
39 fmc_pr(QE_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval); in spi_xtx_set_op()
43 fmc_pr(QE_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval); in spi_xtx_set_op()
48 fmc_pr(QE_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval); in spi_xtx_set_op()
67 fmc_pr(QE_DBG, "\t* Start SPI Nor xtx %s Quad.\n", str[op]); in spi_xtx_qe_enable()
71 fmc_pr(QE_DBG, "\t Read Status Register-h[%#x]%#x\n", XTX_READ_SR_H, in spi_xtx_qe_enable()
74 fmc_pr(QE_DBG, "\t* Quad was %s status:%#x\n", str[op], status_h); in spi_xtx_qe_enable()
88 fmc_pr(QE_DBG, "\t Write IO[%p]%#x\n", host->iobase, in spi_xtx_qe_enable()
97 fmc_pr(QE_DBG, "\t Read Status Register-h[%#x]:%#x\n", in spi_xtx_qe_enable()
100 fmc_pr(QE_DBG, "\t %s Quad success. status_h:%#x\n", in spi_xtx_qe_enable()
/third_party/uboot/u-boot-2020.01/drivers/mtd/nand/raw/hifmc100/
Dhifmc100_spi_general.c34 fmc_pr(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg); in spi_nand_set_cmd()
37 fmc_pr(FT_DBG, "\t||||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, addr); in spi_nand_set_cmd()
42 fmc_pr(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg); in spi_nand_set_cmd()
46 fmc_pr(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg); in spi_nand_set_cmd()
54 fmc_pr(FT_DBG, "\t||||-Write IO[%p]%#x\n", host->iobase, in spi_nand_set_cmd()
61 fmc_pr(FT_DBG, "\t||||-Set OP[%#x]%#x\n", FMC_OP, reg); in spi_nand_set_cmd()
74 fmc_pr(SR_DBG, "\n\t\t|*-Start Get Status\n"); in spi_nand_feature_op()
78 fmc_pr(SR_DBG, "\t\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg); in spi_nand_feature_op()
82 fmc_pr(SR_DBG, "\t\t||-Set OP[%#x]%#x\n", FMC_OP, reg); in spi_nand_feature_op()
87 fmc_pr(SR_DBG, "\t\t|*-End Get Status, result: %#x\n", val); in spi_nand_feature_op()
[all …]
Dhifmc100.c39 fmc_pr(EC_DBG, "\t *-Get CFG[%#x]%#x\n", FMC_CFG, config); in hifmc100_ecc0_switch()
61 fmc_pr(EC_DBG, "\t *-Set CFG[%#x]%#x\n", FMC_CFG, config); in hifmc100_ecc0_switch()
96 fmc_pr(DMA_DB, "\t|-Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg); in set_dma_addr_reg()
100 fmc_pr(DMA_DB, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg); in set_dma_addr_reg()
103 fmc_pr(DMA_DB, "\t|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, in set_dma_addr_reg()
108 fmc_pr(DMA_DB, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB, in set_dma_addr_reg()
126 fmc_pr(REG_DB, "|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg); in set_addr_reg()
133 fmc_pr(REG_DB, "|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg); in set_addr_reg()
148 fmc_pr(WR_DBG, "|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg); in set_cs_addr_reg()
165 fmc_pr(REG_DB, "|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg); in set_cs_addr_reg()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/mtd/nand/raw/hifmc100_nand/
Dhifmc100_nand.c40 fmc_pr(DMA_DB, "\t\t *-Start %s page dma transfer\n", op); in hifmc100_dma_transfer()
44 fmc_pr(DMA_DB, "\t\t |-Set ADDR0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg); in hifmc100_dma_transfer()
48 fmc_pr(DMA_DB, "\t\t |-Set ADDR0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg); in hifmc100_dma_transfer()
52 fmc_pr(DMA_DB, "\t\t |-Set ADDR1[%#x]%#x\n", FMC_DMA_SADDR_D1, reg); in hifmc100_dma_transfer()
56 fmc_pr(DMA_DB, "\t\t |-Set ADDR2[%#x]%#x\n", FMC_DMA_SADDR_D2, reg); in hifmc100_dma_transfer()
60 fmc_pr(DMA_DB, "\t\t |-Set ADDR3[%#x]%#x\n", FMC_DMA_SADDR_D3, reg); in hifmc100_dma_transfer()
67 fmc_pr(DMA_DB, "\t\t |-Set OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg); in hifmc100_dma_transfer()
71 fmc_pr(DMA_DB, "\t\t |-Set LEN[%#x]%#x\n", FMC_DMA_LEN, reg); in hifmc100_dma_transfer()
75 fmc_pr(DMA_DB, "\t\t |-Set OP[%#x]%#x\n", FMC_OP, reg); in hifmc100_dma_transfer()
80 fmc_pr(DMA_DB, "\t\t |-Set AHBCTRL[%#x]%#x\n", FMC_DMA_AHB_CTRL, reg); in hifmc100_dma_transfer()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/mtd/
Dhifmc_common.c54 fmc_pr(FMC_INFO, "Check Flash Memory Controller v100 ..."); in hifmc_ip_ver_check()
60 fmc_pr(FMC_INFO, " Found\n"); in hifmc_ip_ver_check()
74 fmc_pr(BT_DBG, "\t|*-Start switch current device type\n"); in hifmc_dev_type_switch()
77 fmc_pr(BT_DBG, "\t||-Switch unknown device type %d\n", type); in hifmc_dev_type_switch()
83 fmc_pr(BT_DBG, "\t||-Get system STATUS[%#x]%#x\n", in hifmc_dev_type_switch()
86 fmc_pr(BT_DBG, "\t||-Init boot device type to %s flash\n", in hifmc_dev_type_switch()
95 fmc_pr(BT_DBG, "\t||-Switch type to %s flash\n", str[type]); in hifmc_dev_type_switch()
97 fmc_pr(BT_DBG, "\t||-Get HIFMC CFG[%#x]%#x\n", FMC_CFG, reg); in hifmc_dev_type_switch()
103 fmc_pr(BT_DBG, "\t||-Set HIFMC CFG[%#x]%#x\n", FMC_CFG, reg); in hifmc_dev_type_switch()
107 fmc_pr(BT_DBG, "\t|*-End switch current device type\n"); in hifmc_dev_type_switch()
Dhifmc_hi3516av300.c54 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
66 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
92 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
98 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
102 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
104 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
132 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
138 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
141 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
142 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3516cv500.c54 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
66 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
92 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
98 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
102 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
104 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
132 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
138 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
141 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
142 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3516dv300.c54 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
66 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
92 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
98 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
102 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
104 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
132 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
138 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
141 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
142 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3516ev300.c67 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
82 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
106 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
112 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
116 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
118 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
144 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
150 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
153 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
154 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3518ev300.c67 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
82 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
106 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
112 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
116 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
118 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
144 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
150 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
153 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
154 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3520dv500.c61 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
73 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
97 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
103 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
107 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
109 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
136 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
142 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
145 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
146 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3516ev200.c67 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
82 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
106 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
112 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
116 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
118 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
144 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
150 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
153 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
154 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3521dv200.c61 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
73 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
97 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
103 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
107 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
109 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
136 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
142 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
145 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
146 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3516dv200.c67 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
82 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
106 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
112 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
116 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
118 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
144 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
150 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
153 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
154 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
Dhifmc_hi3531dv200.c86 fmc_pr(DTR_DB, "\t|||*-get the setting clock value: %#x\n", in hifmc_set_fmc_system_clock()
99 fmc_pr(DTR_DB, "\t|||*-setting system clock [%#x]%#x\n", in hifmc_set_fmc_system_clock()
124 fmc_pr(QE_DBG, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_2x_clock()
130 fmc_pr(QE_DBG, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
134 fmc_pr(DTR_DB, "best system clock for SDR.\n"); in hifmc_get_fmc_best_2x_clock()
136 fmc_pr(QE_DBG, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_2x_clock()
163 fmc_pr(DTR_DB, "\t|||*-matching flash clock %d\n", *clock); in hifmc_get_fmc_best_4x_clock()
169 fmc_pr(DTR_DB, "\t||||-select system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()
172 fmc_pr(DTR_DB, "best system clock for DTR.\n"); in hifmc_get_fmc_best_4x_clock()
173 fmc_pr(DTR_DB, "\t|||*-matched best system clock: %sMHz\n", in hifmc_get_fmc_best_4x_clock()

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