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Searched refs:gate (Results 1 – 25 of 92) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/clk/
Dclk-gate.c46 struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ? in clk_gate_endisable() local
48 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_gate_endisable()
53 if (gate->flags & CLK_GATE_HIWORD_MASK) { in clk_gate_endisable()
54 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
56 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
59 reg = gate->io_gate_val; in clk_gate_endisable()
61 reg = readl(gate->reg); in clk_gate_endisable()
65 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
67 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
70 writel(reg, gate->reg); in clk_gate_endisable()
[all …]
Dclk_sandbox_ccf.c93 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); in clk_gate2_enable() local
95 gate->state = 1; in clk_gate2_enable()
101 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); in clk_gate2_disable() local
103 gate->state = 0; in clk_gate2_disable()
119 struct clk_gate2 *gate; in sandbox_clk_register_gate2() local
123 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sandbox_clk_register_gate2()
124 if (!gate) in sandbox_clk_register_gate2()
127 gate->state = 0; in sandbox_clk_register_gate2()
128 clk = &gate->clk; in sandbox_clk_register_gate2()
132 kfree(gate); in sandbox_clk_register_gate2()
[all …]
Dclk-composite.c63 struct clk *gate = composite->gate; in clk_composite_enable() local
65 return gate_ops->enable(gate); in clk_composite_enable()
73 struct clk *gate = composite->gate; in clk_composite_disable() local
75 gate_ops->disable(gate); in clk_composite_disable()
90 struct clk *gate, in clk_register_composite() argument
127 if (gate && gate_ops) { in clk_register_composite()
133 composite->gate = gate; in clk_register_composite()
137 gate->data = (ulong)composite; in clk_register_composite()
/third_party/uboot/u-boot-2020.01/drivers/clk/imx/
Dclk-gate2.c40 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); in clk_gate2_enable() local
43 reg = readl(gate->reg); in clk_gate2_enable()
44 reg &= ~(3 << gate->bit_idx); in clk_gate2_enable()
45 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
46 writel(reg, gate->reg); in clk_gate2_enable()
53 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); in clk_gate2_disable() local
56 reg = readl(gate->reg); in clk_gate2_disable()
57 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable()
58 writel(reg, gate->reg); in clk_gate2_disable()
85 struct clk_gate2 *gate; in clk_register_gate2() local
[all …]
Dclk-composite-8m.c124 struct clk_gate *gate = NULL; in imx8m_clk_composite_flags() local
147 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx8m_clk_composite_flags()
148 if (!gate) in imx8m_clk_composite_flags()
151 gate->reg = reg; in imx8m_clk_composite_flags()
152 gate->bit_idx = PCG_CGC_SHIFT; in imx8m_clk_composite_flags()
153 gate->flags = flags; in imx8m_clk_composite_flags()
159 &gate->clk, &clk_gate_ops, flags); in imx8m_clk_composite_flags()
166 kfree(gate); in imx8m_clk_composite_flags()
/third_party/uboot/u-boot-2020.01/arch/arm/dts/
Dsocfpga.dtsi303 compatible = "altr,socfpga-gate-clk";
305 clk-gate = <0x60 0>;
317 compatible = "altr,socfpga-gate-clk";
320 clk-gate = <0x60 1>;
325 compatible = "altr,socfpga-gate-clk";
332 compatible = "altr,socfpga-gate-clk";
335 clk-gate = <0x60 2>;
340 compatible = "altr,socfpga-gate-clk";
343 clk-gate = <0x60 3>;
348 compatible = "altr,socfpga-gate-clk";
[all …]
Dam35xx-clocks.dtsi13 compatible = "ti,am35xx-gate-clock";
21 compatible = "ti,gate-clock";
29 compatible = "ti,am35xx-gate-clock";
37 compatible = "ti,gate-clock";
45 compatible = "ti,am35xx-gate-clock";
53 compatible = "ti,gate-clock";
61 compatible = "ti,am35xx-gate-clock";
98 compatible = "ti,wait-gate-clock";
Domap3xxx-clocks.dtsi36 compatible = "ti,gate-clock";
222 compatible = "ti,gate-clock";
264 compatible = "ti,gate-clock";
379 compatible = "ti,gate-clock";
438 compatible = "ti,gate-clock";
466 compatible = "ti,gate-clock";
494 compatible = "ti,gate-clock";
511 compatible = "ti,composite-no-wait-gate-clock";
595 compatible = "ti,composite-gate-clock";
617 compatible = "ti,composite-gate-clock";
[all …]
Domap36xx-clocks.dtsi20 compatible = "ti,hsdiv-gate-clock";
30 compatible = "ti,hsdiv-gate-clock";
39 compatible = "ti,hsdiv-gate-clock";
48 compatible = "ti,hsdiv-gate-clock";
57 compatible = "ti,hsdiv-gate-clock";
66 compatible = "ti,wait-gate-clock";
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi48 compatible = "ti,composite-gate-clock";
109 compatible = "ti,wait-gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,dss-gate-clock";
182 compatible = "ti,gate-clock";
190 compatible = "ti,dss-gate-clock";
Dam43xx-clocks.dtsi109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,gate-clock";
141 compatible = "ti,gate-clock";
149 compatible = "ti,gate-clock";
351 compatible = "ti,gate-clock";
504 compatible = "ti,gate-clock";
512 compatible = "ti,gate-clock";
520 compatible = "ti,gate-clock";
[all …]
Dsocfpga_arria10.dtsi353 compatible = "altr,socfpga-a10-gate-clk";
356 clk-gate = <0x48 1>;
361 compatible = "altr,socfpga-a10-gate-clk";
364 clk-gate = <0x48 2>;
369 compatible = "altr,socfpga-a10-gate-clk";
372 clk-gate = <0x48 3>;
377 compatible = "altr,socfpga-a10-gate-clk";
380 clk-gate = <0x48 0>;
385 compatible = "altr,socfpga-a10-gate-clk";
387 clk-gate = <0xC8 5>;
[all …]
/third_party/uboot/u-boot-2020.01/drivers/clk/sunxi/
Dclk_sunxi.c25 const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id); in sunxi_set_gate() local
28 if (!(gate->flags & CCU_CLK_F_IS_VALID)) { in sunxi_set_gate()
34 clk->id, gate->off, ilog2(gate->bit)); in sunxi_set_gate()
36 reg = readl(priv->base + gate->off); in sunxi_set_gate()
38 reg |= gate->bit; in sunxi_set_gate()
40 reg &= ~gate->bit; in sunxi_set_gate()
42 writel(reg, priv->base + gate->off); in sunxi_set_gate()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/bcm281xx/
Dclk-core.h95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
390 struct bcm_clk_gate gate; member
394 struct bcm_clk_gate gate; member
398 struct bcm_clk_gate gate; member
Dclk-bcm281xx.c131 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
Dclk-core.c83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
105 if (gate_exists(gate)) { in peri_clk_enable()
106 reg = readl(base + cd->gate.offset); in peri_clk_enable()
107 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
108 writel(reg, base + cd->gate.offset); in peri_clk_enable()
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
145 reg = readl(base + cd->gate.offset); in peri_clk_enable()
146 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
147 writel(reg, base + cd->gate.offset); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/bcm235xx/
Dclk-core.h95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
390 struct bcm_clk_gate gate; member
394 struct bcm_clk_gate gate; member
398 struct bcm_clk_gate gate; member
Dclk-bcm235xx.c131 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
Dclk-core.c83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
105 if (gate_exists(gate)) { in peri_clk_enable()
106 reg = readl(base + cd->gate.offset); in peri_clk_enable()
107 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
108 writel(reg, base + cd->gate.offset); in peri_clk_enable()
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
145 reg = readl(base + cd->gate.offset); in peri_clk_enable()
146 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
147 writel(reg, base + cd->gate.offset); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/third_party/uboot/u-boot-2020.01/doc/device-tree-bindings/clock/
Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
27 Example using multiple gate clocks:
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
/third_party/uboot/u-boot-2020.01/drivers/clk/mediatek/
Dclk-mtk.c386 const struct mtk_gate *gate = &priv->gates[clk->id]; in mtk_clk_gate_enable() local
387 u32 bit = BIT(gate->shift); in mtk_clk_gate_enable()
389 switch (gate->flags & CLK_GATE_MASK) { in mtk_clk_gate_enable()
391 writel(bit, priv->base + gate->regs->clr_ofs); in mtk_clk_gate_enable()
394 writel(bit, priv->base + gate->regs->set_ofs); in mtk_clk_gate_enable()
397 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); in mtk_clk_gate_enable()
400 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); in mtk_clk_gate_enable()
413 const struct mtk_gate *gate = &priv->gates[clk->id]; in mtk_clk_gate_disable() local
414 u32 bit = BIT(gate->shift); in mtk_clk_gate_disable()
416 switch (gate->flags & CLK_GATE_MASK) { in mtk_clk_gate_disable()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx7ulp/
Dscg.c169 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
173 gate = SCG_PLL_PFD0_GATE_MASK; in scg_apll_pfd_get_rate()
179 gate = SCG_PLL_PFD1_GATE_MASK; in scg_apll_pfd_get_rate()
185 gate = SCG_PLL_PFD2_GATE_MASK; in scg_apll_pfd_get_rate()
191 gate = SCG_PLL_PFD3_GATE_MASK; in scg_apll_pfd_get_rate()
201 if (reg & gate || !(reg & valid)) in scg_apll_pfd_get_rate()
219 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
223 gate = SCG_PLL_PFD0_GATE_MASK; in scg_spll_pfd_get_rate()
229 gate = SCG_PLL_PFD1_GATE_MASK; in scg_spll_pfd_get_rate()
235 gate = SCG_PLL_PFD2_GATE_MASK; in scg_spll_pfd_get_rate()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/
Drdc-sema.c66 &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
67 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
94 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
98 writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
/third_party/uboot/u-boot-2020.01/drivers/clk/meson/
Daxg.c54 struct meson_gate *gate; in meson_set_gate() local
59 gate = &gates[clk->id]; in meson_set_gate()
61 if (gate->reg == 0) in meson_set_gate()
64 regmap_update_bits(priv->map, gate->reg, in meson_set_gate()
65 BIT(gate->bit), on ? BIT(gate->bit) : 0); in meson_set_gate()
/third_party/uboot/u-boot-2020.01/drivers/clk/uniphier/
Dclk-uniphier-core.c29 const struct uniphier_clk_gate_data *gate) in uniphier_clk_gate_enable() argument
33 val = readl(priv->base + gate->reg); in uniphier_clk_gate_enable()
34 val |= BIT(gate->bit); in uniphier_clk_gate_enable()
35 writel(val, priv->base + gate->reg); in uniphier_clk_gate_enable()
99 parent_id = data->data.gate.parent_id; in uniphier_clk_get_parent_data()
124 uniphier_clk_gate_enable(priv, &data->data.gate); in __uniphier_clk_enable()

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