| /third_party/uboot/u-boot-2020.01/arch/arm/mach-omap2/omap5/ |
| D | hwinit.c | 56 const struct ctrl_ioregs *ioregs; in io_settings_lpddr2() local
58 get_ioregs(&ioregs); in io_settings_lpddr2()
59 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); in io_settings_lpddr2()
60 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); in io_settings_lpddr2()
61 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); in io_settings_lpddr2()
62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); in io_settings_lpddr2()
63 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_lpddr2()
64 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_lpddr2()
65 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); in io_settings_lpddr2()
66 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); in io_settings_lpddr2()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-omap2/am33xx/ |
| D | ddr.c | 398 void config_io_ctrl(const struct ctrl_ioregs *ioregs) in config_io_ctrl() argument
400 if (!ioregs) in config_io_ctrl()
403 writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); in config_io_ctrl()
404 writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); in config_io_ctrl()
405 writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); in config_io_ctrl()
406 writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); in config_io_ctrl()
407 writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); in config_io_ctrl()
409 writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); in config_io_ctrl()
410 writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); in config_io_ctrl()
411 writel(ioregs->emif_sdram_config_ext, in config_io_ctrl()
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| D | emif4.c | 70 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, in config_ddr() argument
80 config_io_ctrl(ioregs); in config_ddr()
91 config_io_ctrl(ioregs); in config_ddr()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pcm051/ |
| D | board.c | 53 const struct ctrl_ioregs ioregs = { variable
92 config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, in sdram_init()
96 const struct ctrl_ioregs ioregs = { variable
135 config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, in sdram_init()
|
| /third_party/uboot/u-boot-2020.01/board/phytec/phycore_am335x_r2/ |
| D | board.c | 43 const struct ctrl_ioregs ioregs = { variable
135 config_ddr(DDR_CLK_MHZ, &ioregs, in sdram_init()
158 config_ddr(DDR_CLK_MHZ, &ioregs, in sdram_init()
|
| /third_party/uboot/u-boot-2020.01/board/compulab/cm_t335/ |
| D | spl.c | 22 const struct ctrl_ioregs ioregs = { variable
99 config_ddr(303, &ioregs, &ddr3_data, in probe_sdram_size()
|
| /third_party/uboot/u-boot-2020.01/board/bosch/guardian/ |
| D | board.c | 156 const struct ctrl_ioregs ioregs = { variable
166 config_ddr(400, &ioregs, in sdram_init()
|
| /third_party/uboot/u-boot-2020.01/board/eets/pdu001/ |
| D | board.c | 223 const struct ctrl_ioregs ioregs = { variable
233 config_ddr(266, &ioregs, &ddr2_data, in sdram_init()
|
| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-am33xx/ |
| D | ddr_defs.h | 364 void config_io_ctrl(const struct ctrl_ioregs *ioregs);
377 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
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| /third_party/uboot/u-boot-2020.01/board/siemens/pxm2/ |
| D | board.c | 71 const struct ctrl_ioregs ioregs = { in board_init_ddr() local
79 config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, in board_init_ddr()
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| /third_party/uboot/u-boot-2020.01/board/siemens/rut/ |
| D | board.c | 76 const struct ctrl_ioregs ioregs = { in board_init_ddr() local
84 config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data, in board_init_ddr()
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| /third_party/uboot/u-boot-2020.01/board/ti/am335x/ |
| D | board.c | 533 const struct ctrl_ioregs ioregs = { variable
573 config_ddr(266, &ioregs, &ddr2_data, in sdram_init()
576 config_ddr(266, &ioregs, &ddr2_data, in sdram_init()
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| /third_party/uboot/u-boot-2020.01/board/tcl/sl50/ |
| D | board.c | 213 const struct ctrl_ioregs ioregs = { variable
|