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Searched refs:main_pll_cntr8clk (Results 1 – 2 of 2) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/include/mach/
Dclock_manager_s10.h40 u32 main_pll_cntr8clk; member
/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/
Dclock_manager_s10.c145 writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk); in cm_basic_init()