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Searched refs:opc (Results 1 – 25 of 92) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrFormats.td35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 let Inst{15-11} = opc;
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 let Inst{31-27} = opc{8-4};
53 let Inst{19-16} = opc{3-0};
60 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
61 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
65 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
[all …]
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/crypto/
Dmilenage.c36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument
44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
67 tmp1[i] ^= opc[i]; in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument
96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345()
108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345()
114 tmp3[i] ^= opc[i]; in milenage_f2345()
124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345()
129 ck[i] ^= opc[i]; in milenage_f2345()
[all …]
Dmilenage.h12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
/third_party/wpa_supplicant/wpa_supplicant-2.9/src/crypto/
Dmilenage.c36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument
44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
67 tmp1[i] ^= opc[i]; in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument
96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345()
108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345()
114 tmp3[i] ^= opc[i]; in milenage_f2345()
124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345()
129 ck[i] ^= opc[i]; in milenage_f2345()
[all …]
Dmilenage.h12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td258 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
269 let Inst{18-17} = opc{2-1};
270 let Inst{16} = opc{0};
276 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
279 multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
280 def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
281 def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
282 def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
283 def _D : sve_int_ptrue<0b11, opc, asm, PPR64, nxv2i1, op>;
385 class sve_int_pfalse<bits<6> opc, string asm>
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DAArch64InstrFormats.td1244 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
1251 let Inst{7-5} = opc;
1442 // case opc of
1449 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1453 let Inst{24-21} = opc;
1459 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1460 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1466 class SpecialReturn<bits<4> opc, string asm>
1467 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1503 class AuthOneOperand<bits<3> opc, bits<1> M, string asm>
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrFormats.td548 string opc, string asm, string cstr,
555 let AsmString = !strconcat(opc, "${p}", asm);
563 string opc, string asm, string cstr,
568 let AsmString = !strconcat(opc, asm);
579 string opc, string asm, string cstr,
589 let AsmString = !strconcat(opc, "${s}${p}", asm);
607 string opc, string asm, list<dag> pattern>
609 opc, asm, "", pattern>;
611 string opc, string asm, list<dag> pattern>
613 opc, asm, "", pattern>;
[all …]
DARMInstrThumb2.td436 string opc, string asm, list<dag> pattern>
437 : T2I<oops, iops, itin, opc, asm, pattern> {
449 string opc, string asm, list<dag> pattern>
450 : T2sI<oops, iops, itin, opc, asm, pattern> {
462 string opc, string asm, list<dag> pattern>
463 : T2I<oops, iops, itin, opc, asm, pattern> {
475 string opc, string asm, list<dag> pattern>
476 : T2I<oops, iops, itin, opc, asm, pattern> {
488 string opc, string asm, list<dag> pattern>
489 : T2sI<oops, iops, itin, opc, asm, pattern> {
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/third_party/skia/third_party/externals/spirv-cross/reference/shaders-msl-no-opt/asm/tesc/
Dcopy-memory-control-point.asm.tesc75 …Id, device half (&gl_TessLevelOuter)[3], thread spvUnsafeArray<float4, 4>& opc, constant cb1_struc…
79 opc[as_type<int>(r0.x)].x = cb0_0._m0[0u].x;
80 v_48 = opc[0u];
81 v_49 = opc[1u];
82 v_50 = opc[2u];
93 void fork1(device half &gl_TessLevelInner, thread spvUnsafeArray<float4, 4>& opc, constant cb1_stru…
95 opc[3u].x = cb0_0._m0[0u].x;
96 v_56 = opc[3u];
115 spvUnsafeArray<float4, 4> opc;
119 fork0(0u, spvTessLevel[gl_PrimitiveID].edgeTessellationFactor, opc, cb0_0, v_48, v_49, v_50);
[all …]
/third_party/libunwind/src/ia64/
DGscript.c243 enum ia64_script_insn_opcode opc; in compile_reg() local
251 opc = IA64_INSN_MOVE; in compile_reg()
262 opc = IA64_INSN_MOVE_STACKED_NAT; in compile_reg()
264 opc = IA64_INSN_MOVE_STACKED; in compile_reg()
272 opc = IA64_INSN_MOVE_NAT; in compile_reg()
278 opc = IA64_INSN_MOVE_SCRATCH_NAT; in compile_reg()
280 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
299 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
309 opc = IA64_INSN_MOVE_NO_NAT; in compile_reg()
313 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
[all …]
/third_party/skia/third_party/externals/spirv-cross/reference/shaders-no-opt/asm/tesc/
Dcopy-memory-control-point.asm.tesc15 vec4 opc[4];
33 opc[floatBitsToInt(r0.x)].x = cb0_0._m0[0u].x;
34 _48 = opc[0u];
35 _49 = opc[1u];
36 _50 = opc[2u];
47 opc[3u].x = cb0_0._m0[0u].x;
48 _56 = opc[3u];
/third_party/uboot/u-boot-2020.01/drivers/mmc/
Dsh_mmcif.c337 u32 opc = cmd->cmdidx; in sh_mmcif_set_cmd() local
358 if (opc == MMC_CMD_SWITCH) in sh_mmcif_set_cmd()
380 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || in sh_mmcif_set_cmd()
381 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) in sh_mmcif_set_cmd()
384 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || in sh_mmcif_set_cmd()
385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { in sh_mmcif_set_cmd()
390 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd()
391 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) in sh_mmcif_set_cmd()
394 if (opc == MMC_CMD_SEND_OP_COND) in sh_mmcif_set_cmd()
397 if (opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd()
[all …]
Dsh_sdhi.c477 struct mmc_data *data, unsigned short opc) in sh_sdhi_set_cmd() argument
482 return opc | BIT(6); in sh_sdhi_set_cmd()
485 switch (opc) { in sh_sdhi_set_cmd()
487 return opc | (data ? 0x1c00 : 0x40); in sh_sdhi_set_cmd()
489 return opc | (data ? 0x1c00 : 0); in sh_sdhi_set_cmd()
491 return opc | 0x0700; in sh_sdhi_set_cmd()
495 return opc; in sh_sdhi_set_cmd()
500 struct mmc_data *data, unsigned short opc) in sh_sdhi_data_trans() argument
504 switch (opc) { in sh_sdhi_data_trans()
510 opc); in sh_sdhi_data_trans()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrAVX512.td1100 multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
1121 multiclass avx512_broadcast_rm_split<bits<8> opc, string OpcodeStr,
1131 def r : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst), (ins SrcInfo.RC:$src),
1139 def rkz : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
1152 def rk : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
1167 def m : AVX512PI<opc, MRMSrcMem, (outs MaskInfo.RC:$dst),
1178 def mkz : AVX512PI<opc, MRMSrcMem, (outs MaskInfo.RC:$dst),
1194 def mk : AVX512PI<opc, MRMSrcMem, (outs MaskInfo.RC:$dst),
1211 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr, string Name,
1216 avx512_broadcast_rm_split<opc, OpcodeStr, Name, SchedRR, SchedRM,
[all …]
DX86InstrXOP.td13 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
14 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
17 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
48 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
54 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
56 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
59 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
65 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
[all …]
DX86InstrMPX.td18 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
19 def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
22 def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
29 multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
30 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
33 def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
37 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
40 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
DX86InstrFMA.td36 multiclass fma3p_rm_213<bits<8> opc, string OpcodeStr, RegisterClass RC,
39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
47 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
56 multiclass fma3p_rm_231<bits<8> opc, string OpcodeStr, RegisterClass RC,
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
67 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
76 multiclass fma3p_rm_132<bits<8> opc, string OpcodeStr, RegisterClass RC,
80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
89 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
177 multiclass fma3s_rm_213<bits<8> opc, string OpcodeStr,
[all …]
DX86Instr3DNow.td28 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn,
32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
36 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
43 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn,
45 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
49 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
DX86InstrMMX.td33 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
36 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
43 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
51 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
60 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
75 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
77 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
82 def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
91 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
[all …]
DX86InstrSSE.td20 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
33 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
43 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr,
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
56 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
66 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
72 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
79 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
89 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEInstrInfo.td113 multiclass RMm<string opcStr, bits<8>opc,
116 opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, immOp2:$imm32),
123 opc, (outs RC:$sx), (ins immOp2:$imm32),
135 multiclass RRmrr<string opcStr, bits<8>opc,
138 def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
143 multiclass RRmri<string opcStr, bits<8>opc,
148 def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),
153 multiclass RRmiz<string opcStr, bits<8>opc,
156 def zi : RR<opc, (outs RCo:$sx), (ins immOp:$sy),
161 multiclass RRNDmrm<string opcStr, bits<8>opc,
[all …]
/third_party/mingw-w64/mingw-w64-headers/include/
Devntprov.h154 …NT_DESCRIPTOR ev, USHORT Id, UCHAR ver, UCHAR ch, UCHAR lvl, USHORT t, UCHAR opc, ULONGLONG keyw) { in EventDescCreate() argument
160 ev->Opcode = opc; in EventDescCreate()
217 FORCEINLINE PEVENT_DESCRIPTOR EventDescSetOpcode (PEVENT_DESCRIPTOR ev, UCHAR opc) { in EventDescSetOpcode() argument
218 ev->Opcode = opc; in EventDescSetOpcode()
/third_party/uboot/u-boot-2020.01/common/
Dbedbug.c756 struct opcode *opc; in asmppc() local
776 if ((opc = find_opcode_by_name (scratch)) == (struct opcode *) 0) { in asmppc()
783 printf ("asmppc: Opcode = \"%s\"\n", opc->name); in asmppc()
787 if (opc->fields[i] == 0) in asmppc()
796 instr = opc->opcode; in asmppc()
801 oper[n_operands] = &operands[opc->fields[n_operands] - 1]; in asmppc()
823 if ((param = parse_operand (memaddr, opc, oper[n_operands], in asmppc()
855 int parse_operand (unsigned long memaddr, struct opcode *opc, in parse_operand() argument
869 if (opc->hint & H_RELATIVE) in parse_operand()
/third_party/openssl/crypto/bio/
Dbss_log.c369 opcdef_p->opc$b_ms_type = OPC$_RQ_RQST; in xsyslog()
370 memcpy(opcdef_p->opc$z_ms_target_classes, &VMS_OPC_target, 3); in xsyslog()
371 opcdef_p->opc$l_ms_rqstid = 0; in xsyslog()
372 memcpy(&opcdef_p->opc$l_ms_text, buf, len); in xsyslog()

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