Home
last modified time | relevance | path

Searched refs:pbs_mode (Results 1 – 2 of 2) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/a38x/
Dddr3_training_pbs.c36 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode) in ddr3_tip_pbs() argument
42 (pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH; in ddr3_tip_pbs()
43 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE; in ddr3_tip_pbs()
44 int iterations = (pbs_mode == PBS_RX_MODE) ? 31 : 63; in ddr3_tip_pbs()
45 u32 res_valid_mask = (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f; in ddr3_tip_pbs()
72 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
85 validation_val = (pbs_mode == PBS_RX_MODE) ? 0x1f : 0; in ddr3_tip_pbs()
91 (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f; in ddr3_tip_pbs()
144 (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
166 (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
[all …]
Dddr3_init.h179 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
180 int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);