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Searched refs:per_pll_cntr4clk (Results 1 – 2 of 2) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/include/mach/
Dclock_manager_s10.h52 u32 per_pll_cntr4clk; member
/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/
Dclock_manager_s10.c149 writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk); in cm_basic_init()