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Searched refs:pllc1 (Results 1 – 2 of 2) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/
Dclock_manager_s10.c75 writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); in cm_basic_init()
97 writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); in cm_basic_init()
281 clock /= (readl(&clock_manager_base->main_pll.pllc1) & in cm_get_l3_main_clk_hz()
287 clock /= (readl(&clock_manager_base->per_pll.pllc1) & in cm_get_l3_main_clk_hz()
/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/include/mach/
Dclock_manager_s10.h95 u32 pllc1; member
122 u32 pllc1; member