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Searched refs:reg_base (Results 1 – 25 of 57) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/spi/
Dcadence_qspi_apb.c167 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
168 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
171 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
172 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
188 void cadence_qspi_apb_controller_enable(void *reg_base) in cadence_qspi_apb_controller_enable() argument
191 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
193 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
196 void cadence_qspi_apb_controller_disable(void *reg_base) in cadence_qspi_apb_controller_disable() argument
199 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
201 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
[all …]
Dcadence_qspi.h72 void cadence_qspi_apb_chipselect(void *reg_base,
74 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
75 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
77 void cadence_qspi_apb_delay(void *reg_base,
81 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
82 void cadence_qspi_apb_readdata_capture(void *reg_base,
Datmel_spi.c242 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_claim_bus() local
262 writel(csrx, &reg_base->csr[cs]); in atmel_spi_claim_bus()
269 writel(mode, &reg_base->mr); in atmel_spi_claim_bus()
271 writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); in atmel_spi_claim_bus()
321 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_xfer() local
363 readl(&reg_base->rdr); in atmel_spi_xfer()
367 status = readl(&reg_base->sr); in atmel_spi_xfer()
377 writel(value, &reg_base->tdr); in atmel_spi_xfer()
382 value = readl(&reg_base->rdr); in atmel_spi_xfer()
395 wait_for_bit_le32(&reg_base->sr, in atmel_spi_xfer()
/third_party/uboot/u-boot-2020.01/drivers/ata/
Dahci_sunxi.c17 static int sunxi_ahci_phy_init(u8 *reg_base) in sunxi_ahci_phy_init() argument
22 writel(0, reg_base + AHCI_RWCR); in sunxi_ahci_phy_init()
25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()
26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); in sunxi_ahci_phy_init()
33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in sunxi_ahci_phy_init()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/mmc/
Dkona_sdhci.c81 void *reg_base; in kona_sdhci_init() local
91 reg_base = (void *)CONFIG_SYS_SDIO_BASE0; in kona_sdhci_init()
92 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, in kona_sdhci_init()
96 reg_base = (void *)CONFIG_SYS_SDIO_BASE1; in kona_sdhci_init()
97 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, in kona_sdhci_init()
101 reg_base = (void *)CONFIG_SYS_SDIO_BASE2; in kona_sdhci_init()
102 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, in kona_sdhci_init()
106 reg_base = (void *)CONFIG_SYS_SDIO_BASE3; in kona_sdhci_init()
107 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, in kona_sdhci_init()
121 host->ioaddr = reg_base; in kona_sdhci_init()
Ddavinci_mmc.c31 struct davinci_mmc_regs *reg_base; /* Register base address */ member
56 struct davinci_mmc_regs *regs = host->reg_base;
162 volatile struct davinci_mmc_regs *regs = host->reg_base;
355 struct davinci_mmc_regs *regs = host->reg_base;
391 struct davinci_mmc_regs *regs = host->reg_base;
398 struct davinci_mmc_regs *regs = host->reg_base;
501 priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
520 priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
/third_party/uboot/u-boot-2020.01/arch/arm/mach-uniphier/clk/
Dpll-base-ld20.c32 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, in uniphier_ld20_sscpll_init() argument
35 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_init()
63 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) in uniphier_ld20_sscpll_ssc_en() argument
65 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_ssc_en()
75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
77 void __iomem *base = sc_base + reg_base; in uniphier_ld20_sscpll_set_regi()
88 int uniphier_ld20_vpll27_init(unsigned long reg_base) in uniphier_ld20_vpll27_init() argument
90 void __iomem *base = sc_base + reg_base; in uniphier_ld20_vpll27_init()
108 int uniphier_ld20_dspll_init(unsigned long reg_base) in uniphier_ld20_dspll_init() argument
110 void __iomem *base = sc_base + reg_base; in uniphier_ld20_dspll_init()
Dpll.h14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
18 int uniphier_ld20_vpll27_init(unsigned long reg_base);
19 int uniphier_ld20_dspll_init(unsigned long reg_base);
/third_party/uboot/u-boot-2020.01/drivers/net/pfe_eth/
Dpfe_mdio.c19 void *reg_base = bus->priv; in pfe_write_addr() local
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
35 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { in pfe_write_addr()
45 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_write_addr()
53 void *reg_base = bus->priv; in pfe_phy_read() local
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
83 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { in pfe_phy_read()
93 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_read()
98 val = (u16)readl(reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
99 debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base, in pfe_phy_read()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/usb/musb-new/
Dda8xx.c66 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt() local
79 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); in da8xx_musb_interrupt()
83 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); in da8xx_musb_interrupt()
99 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); in da8xx_musb_interrupt()
143 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_interrupt()
153 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init() local
174 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); in da8xx_musb_init()
195 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable() local
202 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); in da8xx_musb_enable()
205 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, in da8xx_musb_enable()
[all …]
Dam35x.c94 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
101 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
102 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); in am35x_musb_enable()
106 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
118 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
120 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); in am35x_musb_disable()
121 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
124 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
226 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
251 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); in am35x_musb_interrupt()
[all …]
Dmusb_dsps.c158 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
166 dsps_writel(reg_base, wrp->epintr_set, epmask); in dsps_musb_enable()
167 dsps_writel(reg_base, wrp->coreintr_set, coremask); in dsps_musb_enable()
171 dsps_writel(reg_base, wrp->coreintr_set, in dsps_musb_enable()
188 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
190 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); in dsps_musb_disable()
191 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
194 dsps_writel(reg_base, wrp->eoi, 0); in dsps_musb_disable()
295 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
311 epintr = dsps_readl(reg_base, wrp->epintr_status); in dsps_interrupt()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/pci_endpoint/
Dpcie-cadence.h230 void __iomem *reg_base; member
238 writeb(value, pcie->reg_base + reg); in cdns_pcie_writeb()
243 writew(value, pcie->reg_base + reg); in cdns_pcie_writew()
248 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
253 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
260 writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writeb()
266 writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writew()
272 writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writel()
279 writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writeb()
285 writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writew()
[all …]
/third_party/libffi/src/avr32/
Dffi.c72 char *reg_base = stack; in ffi_prep_args() local
82 *(void**)reg_base = ecif->rvalue; in ffi_prep_args()
111 addr = reg_base + (index * 4); in ffi_prep_args()
118 addr = reg_base + 4; in ffi_prep_args()
123 addr = reg_base + 12; in ffi_prep_args()
166 printf("r%d: 0x%08x\n", 12 - i, ((unsigned int*)reg_base)[i]); in ffi_prep_args()
275 register char *reg_base = stack; in ffi_prep_incoming_args_SYSV() local
290 *rvalue = *(void **)reg_base; in ffi_prep_incoming_args_SYSV()
320 *p_argv = (void*)reg_base + (index * 4); in ffi_prep_incoming_args_SYSV()
327 *p_argv = (void*)reg_base + 4; in ffi_prep_incoming_args_SYSV()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/mailbox/
Dstm32-ipcc.c33 void __iomem *reg_base; member
110 ipcc->reg_base = (void __iomem *)addr; in stm32_ipcc_probe()
126 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
137 ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR); in stm32_ipcc_probe()
/third_party/uboot/u-boot-2020.01/include/
Dhicpu_common.h52 extern int himci_add_port(int index, u32 reg_base, u32 freq);
56 extern int himci_add_port(int index, u32 reg_base, u32 freq);
/third_party/uboot/u-boot-2020.01/drivers/pinctrl/
Dpinctrl-at91-pio4.c25 struct atmel_pio4_port *reg_base; member
99 (struct atmel_pio4_port *)((u32)plat->reg_base + in atmel_pio4_bank_base()
164 plat->reg_base = (struct atmel_pio4_port *)addr_base; in atmel_pinctrl_probe()
/third_party/uboot/u-boot-2020.01/drivers/clk/at91/
Dclk-plladiv.c22 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_get_rate()
41 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_set_rate()
Dpmc.c41 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev); in at91_pmc_core_probe()
116 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev_pmc); in at91_clk_probe()
Dclk-usb.c26 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_get_rate()
47 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_set_rate()
/third_party/uboot/u-boot-2020.01/board/freescale/ls1012afrdm/
Deth.c54 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; in pfe_eth_board_init()
67 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; in pfe_eth_board_init()
/third_party/boost/libs/type_index/test/
Dtype_index_runtime_cast_test.cpp100 struct reg_base { struct
104 struct reg_derived : reg_base {
105 BOOST_TYPE_INDEX_REGISTER_RUNTIME_CLASS((reg_base))
276 reg_base* rb = &rd; in register_runtime_class()
/third_party/uboot/u-boot-2020.01/product/hiosd/dec/
Djpegd_drv.h182 void jpegd_drv_write_regs(S_JPGD_REGS_TYPE *reg_base, jpegd_vpu_config *vpu_config);
184 void jpegd_drv_read_regs(S_JPGD_REGS_TYPE *reg_base, jpegd_vpu_status *vpu_status);
Djpegd.h221 void jpegd_write_regs(jpegd_handle handle, S_JPGD_REGS_TYPE *reg_base);
222 void jpegd_read_regs(jpegd_handle handle, S_JPGD_REGS_TYPE *reg_base);
/third_party/uboot/u-boot-2020.01/drivers/pci/
Dpci_ftpci100.c19 unsigned int reg_base; member
228 priv->reg_base = CONFIG_FTPCI100_BASE; in ftpci_preinit()
233 ftpci100 = (struct ftpci100_ahbc *)priv->reg_base; in ftpci_preinit()

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