Searched refs:reg_ctrl (Results 1 – 5 of 5) sorted by relevance
| /third_party/uboot/u-boot-2020.01/drivers/spi/ |
| D | mxc_spi.c | 153 s32 reg_ctrl, reg_config; in spi_cfg_mxc() local
165 reg_ctrl = MXC_CSPICTRL_MODE_MASK; in spi_cfg_mxc()
166 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
167 reg_ctrl |= MXC_CSPICTRL_EN; in spi_cfg_mxc()
168 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
188 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | in spi_cfg_mxc()
190 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | in spi_cfg_mxc()
192 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | in spi_cfg_mxc()
221 debug("reg_ctrl = 0x%x\n", reg_ctrl); in spi_cfg_mxc()
222 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-sunxi/ |
| D | display.h | 139 u32 reg_ctrl; /* 0x870 */ member
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx6/ |
| D | ddr.c | 60 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) in modify_dg_result() argument
69 val_ctrl = readl(reg_ctrl); in modify_dg_result()
84 writel(val_ctrl, reg_ctrl); in modify_dg_result()
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| /third_party/uboot/u-boot-2020.01/drivers/net/ |
| D | e1000.c | 1722 uint32_t reg_ctrl, reg_ctrl_ext; in e1000_initialize_hardware_bits() local
1772 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1773 reg_ctrl &= ~(1 << 29); in e1000_initialize_hardware_bits()
1776 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
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| /third_party/uboot/u-boot-2020.01/drivers/video/sunxi/ |
| D | sunxi_display.c | 520 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); in sunxi_composer_enable()
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