Searched refs:rpu_base (Results 1 – 4 of 4) sorted by relevance
32 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_halt_mode()37 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_halt_mode()40 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_halt_mode()45 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_halt_mode()53 tmp = readl(&rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()64 writel(tmp, &rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
59 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_halt_mode()64 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_halt_mode()67 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_halt_mode()72 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_halt_mode()80 tmp = readl(&rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()91 writel(tmp, &rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()171 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_start()176 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_start()178 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_start()183 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_start()
53 #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR) macro
99 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) macro