Searched refs:timing_cfg_9 (Results 1 – 6 of 6) sorted by relevance
92 .timing_cfg_9 = 0,
86 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ member
282 unsigned int timing_cfg_9; member
165 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); in fsl_ddr_set_memctl_regs()
2112 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9()2115 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
665 CFG_REGS(timing_cfg_9), in print_fsl_memctl_config_regs()756 CFG_REGS(timing_cfg_9), in fsl_ddr_regs_edit()