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Searched refs:tmp_count (Results 1 – 4 of 4) sorted by relevance

/third_party/ffmpeg/libswresample/tests/
Dswresample.c346 int tmp_count; in main() local
351 shift(amid, mid_count, out_ch_count, out_sample_fmt); tmp_count = mid_count; in main()
353 shift(amid, mid_count-tmp_count, out_ch_count, out_sample_fmt); tmp_count = mid_count; in main()
356 shift(amid, mid_count-tmp_count, out_ch_count, out_sample_fmt); tmp_count = mid_count; in main()
359 shift(amid, -tmp_count, out_ch_count, out_sample_fmt); in main()
/third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/axp/
Dddr3_init.c199 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
230 tmp_count = 0; in ddr3_save_and_set_training_windows()
250 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
252 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000; in ddr3_save_and_set_training_windows()
253 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
258 win_jump_index * tmp_count, 0); in ddr3_save_and_set_training_windows()
261 tmp_count++; in ddr3_save_and_set_training_windows()
Dddr3_write_leveling.c187 u32 tmp_count, ecc, reg; in ddr3_wl_supplement() local
227 tmp_count = 0; in ddr3_wl_supplement()
264 tmp_count * (SDRAM_CS_SIZE + 1) + in ddr3_wl_supplement()
420 tmp_count++; in ddr3_wl_supplement()
/third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/a38x/
Dmv_ddr_plat.c1142 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
1172 tmp_count = 0; in ddr3_save_and_set_training_windows()
1192 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
1194 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) & in ddr3_save_and_set_training_windows()
1196 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
1201 win_jump_index * tmp_count, 0); in ddr3_save_and_set_training_windows()
1203 tmp_count++; in ddr3_save_and_set_training_windows()