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Searched refs:ud_reg_name (Results 1 – 5 of 5) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/net/hisfv300/
Dmac.c29 old = hieth_readl_bits(ld, ud_reg_name(MAC_PORTSET), BITS_MACSTAT); in _set_linkstat()
30 hieth_writel_bits(ld, mode, ud_reg_name(MAC_PORTSET), BITS_MACSTAT); in _set_linkstat()
39 old = hieth_readl_bits(ld, ud_reg_name(MAC_PORTSEL), BITS_NEGMODE); in _set_negmode()
40 hieth_writel_bits(ld, mode, ud_reg_name(MAC_PORTSEL), BITS_NEGMODE); in _set_negmode()
49 val = hieth_readl_bits(ld, ud_reg_name(MAC_PORTSEL), BITS_NEGMODE); in _get_negmode()
65 val = hieth_readl_bits(ld, ud_reg_name(MAC_RO_STAT), BITS_MACSTAT); in hieth_get_linkstat()
73 (void)hieth_readl_bits(ld, ud_reg_name(MAC_TX_IPGCTRL), in hieth_set_mac_leadcode_cnt_limit()
75 hieth_writel_bits(ld, cnt, ud_reg_name(MAC_TX_IPGCTRL), in hieth_set_mac_leadcode_cnt_limit()
90 (void)hieth_readl_bits(ld, ud_reg_name(MAC_TX_IPGCTRL), BITS_IPG); in hieth_set_mac_trans_interval_bits()
91 hieth_writel_bits(ld, nbits, ud_reg_name(MAC_TX_IPGCTRL), BITS_IPG); in hieth_set_mac_trans_interval_bits()
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Dctrl.h123 #define is_recv_packet_rx(ld) ((hieth_readl(ld, ud_reg_name(GLB_RO_QUEUE_STAT)) >> 8) & 0x3F)
128 #define hw_get_rxpkg_id(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_IQFRM_DES), BITS_RXPKG_ID)
129 #define hw_get_rxpkg_len(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_IQFRM_DES), BITS_RXPKG_LEN)
131 #define hw_get_txqid(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_ID), BITS_TXINQ_ID)
132 #define hw_get_rxqid(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_ID), BITS_RXINQ_ID)
134 #define hw_xmitq_cnt_inuse(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_XMITQ_CNT_…
135 #define hw_recvq_cnt_rxok(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_RECVQ_CNT_R…
137 #define hw_recvq_setfd(ld, fd) hieth_writel(ld, (fd).frm_addr, ud_reg_name(GLB_IQ_ADDR))
Dctrl.c55 return hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), in _test_xmit_queue_ready()
61 return hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), in _test_recv_queue_ready()
135 hieth_writel(ld, fd.frm_addr, ud_reg_name(GLB_EQ_ADDR)); in hw_xmitq_setfd()
136 hieth_writel_bits(ld, fd.frm_len, ud_reg_name(GLB_EQFRM_LEN), BITS_TXINQ_LEN); in hw_xmitq_setfd()
Dnet_drv.c184 hieth_writel_bits(ld, HIETH_HW_TXQ_DEPTH, ud_reg_name(GLB_QLEN_SET), BITS_TXQ_DEP); in hieth_net_open()
187 hieth_writel_bits(ld, HIETH_HW_RXQ_DEPTH, ud_reg_name(GLB_QLEN_SET), BITS_RXQ_DEP); in hieth_net_open()
365 recvq_ready = hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_RECVQ_RDY); in hieth_recv()
379 hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), in hieth_recv()
427 recvq_ready = hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_RECVQ_RDY); in hieth_recv()
479 xmitq_ready = hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_XMITQ_RDY); in hieth_send()
Dhieth.h151 #define ud_reg_name(name) ((ld->port == UP_PORT) ? U_##name : D_##name) macro