| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another…
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
44 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
50 "BriefDescription": "L1 Cache evictions for dirty data"
54 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
60 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
86 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
44 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
50 "BriefDescription": "L1 Cache evictions for dirty data"
54 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
60 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
85 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
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| D | memory.json | 36 … for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM syst…
44 … for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM syst…
49 … for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM syst…
57 … for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM syst…
62 …cription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-DRAM syst…
70 …cription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-DRAM syst…
75 …cription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets…
83 …cription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets…
88 …iption": "Counts requests to the uncore subsystem that miss the L2 cache and targets non-DRAM syst…
96 …iption": "Counts requests to the uncore subsystem that miss the L2 cache and targets non-DRAM syst…
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
9 …LB refill. This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes r…
15 …"PublicDescription": "L1 data cache refill. This event counts any load or store operation or page …
18 "BriefDescription": "L1 data cache refill"
21 …tion": "L1 data cache access. This event counts any load or store operation or page table walk acc…
24 "BriefDescription": "L1 data cache access"
27 … data TLB refill. This event counts any refill of the data L1 TLB from the L2 TLB. This includes r…
33 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac…
36 "BriefDescription": "L1 instruction cache access"
[all …]
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
12 "BriefDescription": "L2 cache request misses"
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
24 "BriefDescription": "L2 cache requests"
28 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
52 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
60 "BriefDescription": "L1 Cache evictions for dirty data"
64 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
72 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
100 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
12 "BriefDescription": "L2 cache request misses"
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
24 "BriefDescription": "L2 cache requests"
28 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
52 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
60 "BriefDescription": "L1 Cache evictions for dirty data"
64 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
72 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
101 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | fsl_85xx_l2ctlr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
5 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
27 return -EINVAL; in get_cache_sram_params()
30 return -EINVAL; in get_cache_sram_params()
32 sram_params->sram_offset = addr; in get_cache_sram_params()
33 sram_params->sram_size = size; in get_cache_sram_params()
56 __setup("cache-sram-size=", get_size_from_cmdline);
57 __setup("cache-sram-offset=", get_offset_from_cmdline);
68 if (!dev->dev.of_node) { in mpc85xx_l2ctlr_of_probe()
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| /kernel/linux/linux-4.19/arch/powerpc/sysdev/ |
| D | fsl_85xx_l2ctlr.c | 2 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
40 return -EINVAL; in get_cache_sram_params()
43 return -EINVAL; in get_cache_sram_params()
45 sram_params->sram_offset = addr; in get_cache_sram_params()
46 sram_params->sram_size = size; in get_cache_sram_params()
69 __setup("cache-sram-size=", get_size_from_cmdline);
70 __setup("cache-sram-offset=", get_offset_from_cmdline);
81 if (!dev->dev.of_node) { in mpc85xx_l2ctlr_of_probe()
82 dev_err(&dev->dev, "Device's OF-node is NULL\n"); in mpc85xx_l2ctlr_of_probe()
[all …]
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local…
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.txt | 1 * ARM L2 Cache Controller
4 PL310 and variants) based level 2 cache controller. All these various implementations
5 of the L2 cache controller have compatible programming models (Note 1).
6 Some of the properties that are just prefixed "cache-*" are taken from section
10 The ARM L2 cache representation in the device tree should be done as follows:
14 - compatible : should be one of:
15 "arm,pl310-cache"
16 "arm,l220-cache"
17 "arm,l210-cache"
18 "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejecte…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …n": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …n": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejecte…
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejecte…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …n": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …n": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejecte…
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/uniphier/ |
| D | cache-uniphier.txt | 1 UniPhier outer cache controller
3 UniPhier SoCs are integrated with a full-custom outer cache controller system.
4 All of them have a level 2 cache controller, and some have a level 3 cache
8 - compatible: should be "socionext,uniphier-system-cache"
9 - reg: offsets and lengths of the register sets for the device. It should
12 - cache-unified: specifies the cache is a unified cache.
13 - cache-size: specifies the size in bytes of the cache
14 - cache-sets: specifies the number of associativity sets of the cache
15 - cache-line-size: specifies the line size in bytes
16 - cache-level: specifies the level in the cache hierarchy. The value should
[all …]
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
[all …]
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 3 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
10 "BriefDescription": "Demand Data Read miss L2, no rejects",
14 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
20 "BriefDescription": "RFO requests that miss L2 cache",
24 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
30 "BriefDescription": "L2 cache misses when fetching instructions",
34 "PublicDescription": "Demand requests that miss L2 cache.",
41 "BriefDescription": "Demand requests that miss L2 cache",
45 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
51 "BriefDescription": "L2 prefetch requests that miss L2 cache",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 3 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
10 "BriefDescription": "Demand Data Read miss L2, no rejects",
14 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
20 "BriefDescription": "RFO requests that miss L2 cache",
24 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
30 "BriefDescription": "L2 cache misses when fetching instructions",
34 "PublicDescription": "Demand requests that miss L2 cache.",
41 "BriefDescription": "Demand requests that miss L2 cache",
45 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
51 "BriefDescription": "L2 prefetch requests that miss L2 cache",
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx-l2c.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
42 /* Based on 128 byte cache line size */
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
159 * Configure one of the four L2 Cache performance counters to capture event
163 * @event: The type of L2 Cache event occurrence to count.
173 * Read the given L2 Cache performance counter. The counter must be configured
[all …]
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