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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
[all …]
Daxc003.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
[all …]
Dvdk_axs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&mb_intc>;
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 #clock-cells = <0>;
24 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-4.19/arch/arc/boot/dts/
Daxs10x_mb.dtsi4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
21 interrupt-parent = <&mb_intc>;
23 creg_rst: reset-controller@11220 {
24 compatible = "snps,axs10x-reset";
25 #reset-cells = <1>;
30 compatible = "snps,axs10x-i2s-pll-clock";
33 #clock-cells = <0>;
[all …]
Daxc003.dtsi2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
27 input_clk: input-clk {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <33333333>;
[all …]
Daxc001.dtsi2 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
18 #address-cells = <2>;
19 #size-cells = <2>;
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <750000000>;
34 core_intc: arc700-intc@cpu {
[all …]
Dvdk_axc003.dtsi17 #address-cells = <1>;
18 #size-cells = <1>;
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <50000000>;
33 core_intc: archs-intc@cpu {
34 compatible = "snps,archs-intc";
[all …]
Dvdk_axc003_idu.dtsi18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <50000000>;
34 core_intc: archs-intc@cpu {
35 compatible = "snps,archs-intc";
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.txt1 * Synopsys DesignWare ABP UART
4 - compatible : "snps,dw-apb-uart"
5 - reg : offset and length of the register set for the device.
6 - interrupts : should contain uart interrupt.
10 - clock-frequency : the input clock frequency for the UART.
11 - clocks : phandle to the input clock
14 - clock-names: tuple listing input clock names.
18 - snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
19 configuration parameter. Define this if your UART does not implement the busy
21 - resets : phandle to the parent reset controller.
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/bitmain/
Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dhip01.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <1>;
16 gic: interrupt-controller@1e001000 {
17 compatible = "arm,cortex-a9-gic";
18 #interrupt-cells = <3>;
19 #address-cells = <0>;
20 interrupt-controller;
25 compatible = "fixed-clock";
[all …]
Dbcm11351.dtsi2 * Copyright (C) 2012-2013 Broadcom Corporation
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
17 #include "dt-bindings/clock/bcm281xx.h"
20 #address-cells = <1>;
21 #size-cells = <1>;
24 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a9";
[all …]
Dpicoxcell-pc3x2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm1176jz-s";
18 clock-frequency = <400000000>;
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
[all …]
Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
[all …]
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dhip01.dtsi15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 gic: interrupt-controller@1e001000 {
20 compatible = "arm,cortex-a9-gic";
21 #interrupt-cells = <3>;
22 #address-cells = <0>;
23 interrupt-controller;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
[all …]
Dbcm11351.dtsi2 * Copyright (C) 2012-2013 Broadcom Corporation
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
17 #include "dt-bindings/clock/bcm281xx.h"
24 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a9";
42 compatible = "arm,cortex-a9";
43 enable-method = "brcm,bcm11351-cpu-method";
[all …]
Dpicoxcell-pc3x2.dtsi17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <0>;
22 #size-cells = <0>;
25 compatible = "arm,arm1176jz-s";
27 clock-frequency = <400000000>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
[all …]
Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
[all …]
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]

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