Searched +full:interrupts +full:- +full:extended (Results 1 – 25 of 1048) sorted by relevance
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | integratorap-im-pd1.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 * with the IM-PD1 example logical module mounted.
10 model = "ARM Integrator/AP with IM-PD1";
11 compatible = "arm,integrator-ap";
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
19 /* 1 MB of designated video RAM on the IM-PD1 */
20 compatible = "shared-dma-pool";
22 no-map;
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| D | ste-href-tvk1281618-r2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "ste-href-tvk1281618.dtsi"
13 compatible = "st,lsm303dlh-accel";
14 st,drdy-int-pin = <1>;
15 drive-open-drain;
17 vdd-supply = <&ab8500_ldo_aux1_reg>;
18 vddio-supply = <&db8500_vsmps2_reg>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&accel_tvk_mode>;
22 * These interrupts cannot be used: the other component
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| D | omap3-evm-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/input/input.h>
7 #include "omap-gpmc-smsc911x.dtsi"
12 cpu0-supply = <&vcc>;
18 compatible = "regulator-fixed";
19 regulator-name = "hsusb2_vbus";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
23 startup-delay-us = <70000>;
24 enable-active-high;
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| D | motorola-cpcap-mapphone.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
10 interrupt-parent = <&gpio1>;
11 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
12 interrupt-controller;
13 #interrupt-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 spi-max-frequency = <9600000>;
17 spi-cs-high;
18 spi-cpol;
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| D | armada-38x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | interrupts.txt | 5 -------------------------
7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
16 interrupt-parent = <&intc1>;
17 interrupts = <5 0>, <6 0>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
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| D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
6 specification. The PLIC connects all external interrupts in the system to all
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
13 Each interrupt can be enabled on per-context basis. Any context can claim
16 Each interrupt has a configurable priority. Higher priority interrupts are
17 serviced first. Each context can specify a priority threshold. Interrupts
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
13 specification. The PLIC connects all external interrupts in the system to all
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
[all …]
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| D | interrupts.txt | 5 -------------------------
7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
16 interrupt-parent = <&intc1>;
17 interrupts = <5 0>, <6 0>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | ste-href-tvk1281618.dtsi | 2 * Copyright 2012 ST-Ericsson AB
8 * http://www.opensource.org/licenses/gpl-license.html
14 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "gpio-keys";
19 #address-cells = <1>;
20 #size-cells = <0>;
21 vdd-supply = <&ab8500_ldo_aux1_reg>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
44 interrupt-parent = <&gpio6>;
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| D | motorola-cpcap-mapphone.dtsi | 13 interrupt-parent = <&gpio1>;
14 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
19 spi-max-frequency = <9600000>;
20 spi-cs-high;
21 spi-cpol;
22 spi-cpha;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a-kontron-sl28.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
29 compatible = "gpio-keys";
31 power-button {
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/gpio/ |
| D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | kontron,sl28cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
35 interrupts:
38 interrupt-controller: true
41 "^gpio(@[0-9a-f]+)?$":
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,adsp.txt | 6 - compatible:
10 "qcom,msm8974-adsp-pil"
11 "qcom,msm8996-adsp-pil"
12 "qcom,msm8996-slpi-pil"
14 - interrupts-extended:
16 Value type: <prop-encoded-array>
18 stop-ack IRQs
20 - interrupt-names:
23 Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
25 - clocks:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | mvebu-uart.txt | 2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 - interrupts:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/ |
| D | mvebu-uart.txt | 2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 - interrupts:
[all …]
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| /kernel/linux/linux-5.10/include/linux/rtc/ |
| D | ds1685.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * DS1685/DS1687-series RTC chips.
8 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
11 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
12 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
15 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
16 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
17 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
18 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
29 * struct ds1685_priv - DS1685 private data structure.
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| /kernel/linux/linux-4.19/include/linux/rtc/ |
| D | ds1685.h | 3 * DS1685/DS1687-series RTC chips.
7 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
10 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
11 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
14 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
15 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
16 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
17 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
32 * struct ds1685_priv - DS1685 private data structure.
41 * @prepare_poweroff: pointer to platform pre-poweroff function.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | si4713.txt | 4 supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog
5 and a digital interface, which supports I2S, left-justified and a custom
6 DSP-mode format. It is programmable through an I2C interface.
9 - compatible: Should contain "silabs,si4713"
10 - reg: the I2C address of the device
13 - interrupts-extended: Interrupt specifier for the chips interrupt
14 - reset-gpios: GPIO specifier for the chips reset line
15 - vdd-supply: phandle for Vdd regulator
16 - vio-supply: phandle for Vio regulator
25 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/ |
| D | si4713.txt | 4 supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog
5 and a digital interface, which supports I2S, left-justified and a custom
6 DSP-mode format. It is programmable through an I2C interface.
9 - compatible: Should contain "silabs,si4713"
10 - reg: the I2C address of the device
13 - interrupts-extended: Interrupt specifier for the chips interrupt
14 - reset-gpios: GPIO specifier for the chips reset line
15 - vdd-supply: phandle for Vdd regulator
16 - vio-supply: phandle for Vio regulator
25 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,adsp.txt | 6 - compatible:
10 "qcom,msm8974-adsp-pil"
11 "qcom,msm8996-adsp-pil"
12 "qcom,msm8996-slpi-pil"
13 "qcom,msm8998-adsp-pas"
14 "qcom,msm8998-slpi-pas"
15 "qcom,qcs404-adsp-pas"
16 "qcom,qcs404-cdsp-pas"
17 "qcom,qcs404-wcss-pas"
18 "qcom,sc7180-mpss-pas"
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | atmel-at91.txt | 11 * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
16 o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
18 - "atmel,at91sam9g15"
19 - "atmel,at91sam9g25"
20 - "atmel,at91sam9g35"
21 - "atmel,at91sam9x25"
22 - "atmel,at91sam9x35"
28 * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
30 o "atmel,sama5d2" shall be extended with the specific SoC compatible:
31 - "atmel,sama5d27"
[all …]
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