Searched +full:nand +full:- +full:bus +full:- +full:width (Results 1 – 25 of 597) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to the NAND flash and all accesses
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
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| D | mxc-nand.txt | 4 - compatible: "fsl,imxXX-nand"
5 - reg: address range of the nfc block
6 - interrupts: irq to be used
7 - nand-bus-width: see nand.txt
8 - nand-ecc-mode: see nand.txt
9 - nand-on-flash-bbt: see nand.txt
13 nand@d8000000 {
14 compatible = "fsl,imx27-nand";
17 nand-bus-width = <8>;
18 nand-ecc-mode = "hw";
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
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| D | qcom_nandc.txt | 1 * Qualcomm NAND controller
4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 - reg: MMIO address range
13 - clocks: must contain core clock and always on clock
14 - clock-names: must contain "core" for the core clock and "aon" for the
18 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
[all …]
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| D | gpmc-nand.txt | 3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand.txt
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
[all …]
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| D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand.txt.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
[all …]
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| D | flctl-nand.txt | 1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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| D | nand.txt | 1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
10 Mandatory NAND controller properties:
11 - #address-cells: depends on your controller. Should at least be 1 to
13 - #size-cells: depends on your controller. Put zero unless you need a
16 Optional NAND controller properties
17 - ranges: only needed if you need to define a mapping between CS lines and
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| D | fsmc-nand.txt | 2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to the NAND flash and all accesses
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
[all …]
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| D | qcom_nandc.txt | 1 * Qualcomm NAND controller
4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 - reg: MMIO address range
13 - clocks: must contain core clock and always on clock
14 - clock-names: must contain "core" for the core clock and "aon" for the
18 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
[all …]
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| D | gpmc-nand.txt | 3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
[all …]
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| D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
[all …]
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| D | flctl-nand.txt | 1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
[all …]
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
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| D | fsmc-nand.txt | 2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | omap3430-sdp.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
20 clock-frequency = <2600000>;
32 vmmc-supply = <&vmmc1>;
33 vqmmc-supply = <&vsim>;
35 * S6-3 must be in ON position for 8 bit mode to function
38 bus-width = <8>;
51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
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| D | dra72-evm-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-common.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/ti-dra7-atl.h>
13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
20 stdout-path = &uart1;
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | omap3430-sdp.dts | 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
14 compatible = "ti,omap3430-sdp", "ti,omap3";
23 clock-frequency = <2600000>;
35 vmmc-supply = <&vmmc1>;
36 vqmmc-supply = <&vsim>;
38 * S6-3 must be in ON position for 8 bit mode to function
41 bus-width = <8>;
54 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
58 compatible = "cfi-flash";
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| D | dra72-evm-common.dtsi | 2 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
22 stdout-path = &uart1;
25 evm_12v0: fixedregulator-evm12v0 {
27 compatible = "regulator-fixed";
28 regulator-name = "evm_12v0";
29 regulator-min-microvolt = <12000000>;
[all …]
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| D | at91-som60.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * at91-som60.dtsi - Device Tree file for the SOM60 module
16 stdout-path = &dbgu;
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
107 bus-width = <8>;
115 bus-width = <4>;
120 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
124 atmel,use-dma-rx;
125 atmel,use-dma-tx;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
5 ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
5 ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
[all …]
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