| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | nand.txt | 1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
10 Mandatory NAND controller properties:
11 - #address-cells: depends on your controller. Should at least be 1 to
13 - #size-cells: depends on your controller. Put zero unless you need a
16 Optional NAND controller properties
17 - ranges: only needed if you need to define a mapping between CS lines and
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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| D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand.txt for generic information regarding MTD NAND bindings.
6 - compatible: "oxsemi,ox820-nand"
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
15 nandc: nand-controller@41000000 {
16 compatible = "oxsemi,ox820-nand";
20 #address-cells = <1>;
21 #size-cells = <0>;
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| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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| D | allwinner,sun4i-a10-nand.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller Device Tree Bindings
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
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| D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
6 - compatible: "oxsemi,ox820-nand"
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
15 nandc: nand-controller@41000000 {
16 compatible = "oxsemi,ox820-nand";
20 #address-cells = <1>;
21 #size-cells = <0>;
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| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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| D | mxic-nand.txt | 1 Macronix Raw NAND Controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
6 - reg: should contain 1 entry for the registers
7 - #address-cells: should be set to 1
8 - #size-cells: should be set to 0
9 - interrupts: interrupt line connected to this raw NAND controller
10 - clock-names: should contain "ps", "send" and "send_dly"
11 - clocks: should contain 3 phandles for the "ps", "send" and
15 - children nodes represent the available NAND chips.
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/ |
| D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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| D | davinci_nand.c | 2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
37 #include <linux/platform_data/mtd-davinci.h>
38 #include <linux/platform_data/mtd-davinci-aemif.h>
41 * This is a device driver for the NAND flash controller found on the
46 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
47 * available on chips like the DM355 and OMAP-L137 and needed with the
48 * more error-prone MLC NAND chips.
50 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
51 * outputs in a "wire-AND" configuration, with no per-chip signals.
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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| D | davinci_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
24 #include <linux/platform_data/mtd-davinci.h>
25 #include <linux/platform_data/mtd-davinci-aemif.h>
28 * This is a device driver for the NAND flash controller found on the
33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
34 * available on chips like the DM355 and OMAP-L137 and needed with the
35 * more error-prone MLC NAND chips.
37 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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| D | plat_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic NAND driver
24 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in plat_nand_attach_chip()
26 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip()
27 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip()
37 * Probe for the NAND device.
41 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
49 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
50 return -EINVAL; in plat_nand_probe()
53 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
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| D | socrates_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 * socrates_nand_write_buf - write buffer to chip
33 * @this: NAND chip object
44 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
51 * socrates_nand_read_buf - read chip data into buffer
52 * @this: NAND chip object
65 out_be32(host->io_base, val); in socrates_nand_read_buf()
67 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
73 * socrates_nand_read_byte - read one byte from the chip
84 * Hardware specific access to control-lines
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| D | pasemi_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
8 * Driver for the PWRficient onchip NAND flash interface
33 static const char driver_name[] = "pasemi-nand";
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
42 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); in pasemi_read_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
53 memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); in pasemi_write_buf()
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| D | xway_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
24 * nand commands
25 * The pins of the NAND chip are selected based on the address bits of the
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
76 return readb(data->nandaddr + op); in xway_readb()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm5301x-nand-cs0-bch8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom BCM470X / BCM5301X Nand chip defaults.
5 * This should be included if the NAND controller is on chip select 0
6 * and uses 8 bit ECC.
8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
11 #include "bcm5301x-nand-cs0.dtsi"
14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
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| D | bcm5301x-nand-cs0-bch1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar NAND.
8 #include "bcm5301x-nand-cs0.dtsi"
11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
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| D | bcm5301x-nand-cs0-bch4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "bcm5301x-nand-cs0.dtsi"
9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | bcm5301x-nand-cs0-bch8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom BCM470X / BCM5301X Nand chip defaults.
5 * This should be included if the NAND controller is on chip select 0
6 * and uses 8 bit ECC.
8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
11 #include "bcm5301x-nand-cs0.dtsi"
14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
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| D | bcm5301x-nand-cs0-bch1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar NAND.
8 #include "bcm5301x-nand-cs0.dtsi"
11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
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| D | bcm5301x-nand-cs0-bch4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "bcm5301x-nand-cs0.dtsi"
9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
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| /kernel/linux/linux-5.10/drivers/mtd/nand/ |
| D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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