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Searched refs:div_mask (Results 1 – 6 of 6) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/clk/imx/
Dclk-pllv3.c21 u32 div_mask; member
32 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_get_rate()
43 u32 div_mask) in imx_clk_pllv3() argument
65 pll->div_mask = div_mask; in imx_clk_pllv3()
Dclk.h55 u32 div_mask);
/third_party/uboot/u-boot-2020.01/drivers/clk/mvebu/
Darmada-37xx-periph.c76 u32 div_mask[2]; member
117 .div_mask[0] = 7, \
118 .div_mask[1] = 7, \
132 .div_mask[0] = _m, \
146 .div_mask[0] = _m, \
166 .div_mask[0] = _m, \
181 .div_mask[0] = 7, \
182 .div_mask[1] = 7, \
280 reg = (reg >> clk->div_shift[idx]) & clk->div_mask[idx]; in get_div()
296 reg &= ~(clk->div_mask[idx] << clk->div_shift[idx]); in set_div_val()
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/third_party/uboot/u-boot-2020.01/drivers/clk/
Dclk_sandbox_ccf.c24 u32 div_mask; member
53 u32 div_mask) in sandbox_clk_pllv3() argument
64 pll->div_mask = div_mask; in sandbox_clk_pllv3()
/third_party/uboot/u-boot-2020.01/include/
Dsandbox-clk.h33 u32 div_mask);
/third_party/uboot/u-boot-2020.01/arch/arm/mach-exynos/
Dclock.c23 int32_t div_mask; member
452 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos5_get_periph_rate()
546 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos542x_get_periph_rate()
1516 unsigned div_mask = 0xf, pre_div_mask = 0xff; in exynos5420_set_spi_clk() local
1566 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift); in exynos5420_set_spi_clk()