1Mediatek infracfg controller 2============================ 3 4The Mediatek infracfg controller provides various clocks and reset 5outputs to the system. 6 7Required Properties: 8 9- compatible: Should be one of: 10 - "mediatek,mt2701-infracfg", "syscon" 11 - "mediatek,mt2712-infracfg", "syscon" 12 - "mediatek,mt6797-infracfg", "syscon" 13 - "mediatek,mt7622-infracfg", "syscon" 14 - "mediatek,mt8135-infracfg", "syscon" 15 - "mediatek,mt8173-infracfg", "syscon" 16- #clock-cells: Must be 1 17- #reset-cells: Must be 1 18 19The infracfg controller uses the common clk binding from 20Documentation/devicetree/bindings/clock/clock-bindings.txt 21The available clocks are defined in dt-bindings/clock/mt*-clk.h. 22Also it uses the common reset controller binding from 23Documentation/devicetree/bindings/reset/reset.txt. 24The available reset outputs are defined in 25dt-bindings/reset/mt*-resets.h 26 27Example: 28 29infracfg: power-controller@10001000 { 30 compatible = "mediatek,mt8173-infracfg", "syscon"; 31 reg = <0 0x10001000 0 0x1000>; 32 #clock-cells = <1>; 33 #reset-cells = <1>; 34}; 35