1Texas Instruments sysc interconnect target module wrapper binding 2 3Texas Instruments SoCs can have a generic interconnect target module 4hardware for devices connected to various interconnects such as L3 5interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc 6is mostly used for interaction between module and PRCM. It participates 7in the OCP Disconnect Protocol but other than that is mostly independent 8of the interconnect. 9 10Each interconnect target module can have one or more devices connected to 11it. There is a set of control registers for managing interconnect target 12module clocks, idle modes and interconnect level resets for the module. 13 14These control registers are sprinkled into the unused register address 15space of the first child device IP block managed by the interconnect 16target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. 17 18Required standard properties: 19 20- compatible shall be one of the following generic types: 21 22 "ti,sysc" 23 "ti,sysc-omap2" 24 "ti,sysc-omap4" 25 "ti,sysc-omap4-simple" 26 27 or one of the following derivative types for hardware 28 needing special workarounds: 29 30 "ti,sysc-omap2-timer" 31 "ti,sysc-omap4-timer" 32 "ti,sysc-omap3430-sr" 33 "ti,sysc-omap3630-sr" 34 "ti,sysc-omap4-sr" 35 "ti,sysc-omap3-sham" 36 "ti,sysc-omap-aes" 37 "ti,sysc-mcasp" 38 "ti,sysc-dra7-mcasp" 39 "ti,sysc-usb-host-fs" 40 "ti,sysc-dra7-mcan" 41 42- reg shall have register areas implemented for the interconnect 43 target module in question such as revision, sysc and syss 44 45- reg-names shall contain the register names implemented for the 46 interconnect target module in question such as 47 "rev, "sysc", and "syss" 48 49- ranges shall contain the interconnect target module IO range 50 available for one or more child device IP blocks managed 51 by the interconnect target module, the ranges may include 52 multiple ranges such as device L4 range for control and 53 parent L3 range for DMA access 54 55Optional properties: 56 57- ti,sysc-mask shall contain mask of supported register bits for the 58 SYSCONFIG register as documented in the Technical Reference 59 Manual (TRM) for the interconnect target module 60 61- ti,sysc-midle list of master idle modes supported by the interconnect 62 target module as documented in the TRM for SYSCONFIG 63 register MIDLEMODE bits 64 65- ti,sysc-sidle list of slave idle modes supported by the interconnect 66 target module as documented in the TRM for SYSCONFIG 67 register SIDLEMODE bits 68 69- ti,sysc-delay-us delay needed after OCP softreset before accssing 70 SYSCONFIG register again 71 72- ti,syss-mask optional mask of reset done status bits as described in the 73 TRM for SYSSTATUS registers, typically 1 with some devices 74 having separate reset done bits for children like OHCI and 75 EHCI 76 77- clocks clock specifier for each name in the clock-names as 78 specified in the binding documentation for ti-clkctrl, 79 typically available for all interconnect targets on TI SoCs 80 based on omap4 except if it's read-only register in hwauto 81 mode as for example omap4 L4_CFG_CLKCTRL 82 83- clock-names should contain at least "fck", and optionally also "ick" 84 depending on the SoC and the interconnect target module, 85 some interconnect target modules also need additional 86 optional clocks that can be specified as listed in TRM 87 for the related CLKCTRL register bits 8 to 15 such as 88 "dbclk" or "clk32k" depending on their role 89 90- ti,hwmods optional TI interconnect module name to use legacy 91 hwmod platform data 92 93- ti,no-reset-on-init interconnect target module should not be reset at init 94 95- ti,no-idle-on-init interconnect target module should not be idled at init 96 97Example: Single instance of MUSB controller on omap4 using interconnect ranges 98using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): 99 100 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ 101 compatible = "ti,sysc-omap2"; 102 ti,hwmods = "usb_otg_hs"; 103 reg = <0x2b400 0x4>, 104 <0x2b404 0x4>, 105 <0x2b408 0x4>; 106 reg-names = "rev", "sysc", "syss"; 107 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; 108 clock-names = "fck"; 109 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 110 SYSC_OMAP2_SOFTRESET | 111 SYSC_OMAP2_AUTOIDLE)>; 112 ti,sysc-midle = <SYSC_IDLE_FORCE>, 113 <SYSC_IDLE_NO>, 114 <SYSC_IDLE_SMART>; 115 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 116 <SYSC_IDLE_NO>, 117 <SYSC_IDLE_SMART>, 118 <SYSC_IDLE_SMART_WKUP>; 119 ti,syss-mask = <1>; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0x2b000 0x1000>; 123 124 usb_otg_hs: otg@0 { 125 compatible = "ti,omap4-musb"; 126 reg = <0x0 0x7ff>; 127 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 129 usb-phy = <&usb2_phy>; 130 ... 131 }; 132 }; 133 134Note that other SoCs, such as am335x can have multipe child devices. On am335x 135there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA 136instance as children of a single interconnet target module. 137