1Mediatek display subsystem 2========================== 3 4The Mediatek display subsystem consists of various DISP function blocks in the 5MMSYS register space. The connections between them can be configured by output 6and input selectors in the MMSYS_CONFIG register space. Pixel clock and start 7of frame signal are distributed to the other function blocks by a DISP_MUTEX 8function block. 9 10All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. 11For a description of the MMSYS_CONFIG binding, see 12Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. 13 14DISP function blocks 15==================== 16 17A display stream starts at a source function block that reads pixel data from 18memory and ends with a sink function block that drives pixels on a display 19interface, or writes pixels back to memory. All DISP function blocks have 20their own register space, interrupt, and clock gate. The blocks that can 21access memory additionally have to list the IOMMU and local arbiter they are 22connected to. 23 24For a description of the display interface sink function blocks, see 25Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and 26Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. 27 28Required properties (all function blocks): 29- compatible: "mediatek,<chip>-disp-<function>", one of 30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) 31 "mediatek,<chip>-disp-rdma" - read DMA / line buffer 32 "mediatek,<chip>-disp-wdma" - write DMA 33 "mediatek,<chip>-disp-color" - color processor 34 "mediatek,<chip>-disp-aal" - adaptive ambient light controller 35 "mediatek,<chip>-disp-gamma" - gamma correction 36 "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources 37 "mediatek,<chip>-disp-split" - split stream to two encoders 38 "mediatek,<chip>-disp-ufoe" - data compression engine 39 "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt 40 "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt 41 "mediatek,<chip>-disp-mutex" - display mutex 42 "mediatek,<chip>-disp-od" - overdrive 43 the supported chips are mt2701, mt2712 and mt8173. 44- reg: Physical base address and length of the function block register space 45- interrupts: The interrupt signal from the function block (required, except for 46 merge and split function blocks). 47- clocks: device clocks 48 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 49 For most function blocks this is just a single clock input. Only the DSI and 50 DPI controller nodes have multiple clock inputs. These are documented in 51 mediatek,dsi.txt and mediatek,dpi.txt, respectively. 52 53Required properties (DMA function blocks): 54- compatible: Should be one of 55 "mediatek,<chip>-disp-ovl" 56 "mediatek,<chip>-disp-rdma" 57 "mediatek,<chip>-disp-wdma" 58 the supported chips are mt2701 and mt8173. 59- larb: Should contain a phandle pointing to the local arbiter device as defined 60 in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt 61- iommus: Should point to the respective IOMMU block with master port as 62 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt 63 for details. 64 65Examples: 66 67mmsys: clock-controller@14000000 { 68 compatible = "mediatek,mt8173-mmsys", "syscon"; 69 reg = <0 0x14000000 0 0x1000>; 70 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 71 #clock-cells = <1>; 72}; 73 74ovl0: ovl@1400c000 { 75 compatible = "mediatek,mt8173-disp-ovl"; 76 reg = <0 0x1400c000 0 0x1000>; 77 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 78 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 79 clocks = <&mmsys CLK_MM_DISP_OVL0>; 80 iommus = <&iommu M4U_PORT_DISP_OVL0>; 81 mediatek,larb = <&larb0>; 82}; 83 84ovl1: ovl@1400d000 { 85 compatible = "mediatek,mt8173-disp-ovl"; 86 reg = <0 0x1400d000 0 0x1000>; 87 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 88 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 89 clocks = <&mmsys CLK_MM_DISP_OVL1>; 90 iommus = <&iommu M4U_PORT_DISP_OVL1>; 91 mediatek,larb = <&larb4>; 92}; 93 94rdma0: rdma@1400e000 { 95 compatible = "mediatek,mt8173-disp-rdma"; 96 reg = <0 0x1400e000 0 0x1000>; 97 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 98 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 100 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 101 mediatek,larb = <&larb0>; 102}; 103 104rdma1: rdma@1400f000 { 105 compatible = "mediatek,mt8173-disp-rdma"; 106 reg = <0 0x1400f000 0 0x1000>; 107 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 108 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 110 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 111 mediatek,larb = <&larb4>; 112}; 113 114rdma2: rdma@14010000 { 115 compatible = "mediatek,mt8173-disp-rdma"; 116 reg = <0 0x14010000 0 0x1000>; 117 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 118 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 119 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 120 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 121 mediatek,larb = <&larb4>; 122}; 123 124wdma0: wdma@14011000 { 125 compatible = "mediatek,mt8173-disp-wdma"; 126 reg = <0 0x14011000 0 0x1000>; 127 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 128 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 129 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 130 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 131 mediatek,larb = <&larb0>; 132}; 133 134wdma1: wdma@14012000 { 135 compatible = "mediatek,mt8173-disp-wdma"; 136 reg = <0 0x14012000 0 0x1000>; 137 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 138 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 139 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 140 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 141 mediatek,larb = <&larb4>; 142}; 143 144color0: color@14013000 { 145 compatible = "mediatek,mt8173-disp-color"; 146 reg = <0 0x14013000 0 0x1000>; 147 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 148 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 149 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 150}; 151 152color1: color@14014000 { 153 compatible = "mediatek,mt8173-disp-color"; 154 reg = <0 0x14014000 0 0x1000>; 155 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 156 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 157 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 158}; 159 160aal@14015000 { 161 compatible = "mediatek,mt8173-disp-aal"; 162 reg = <0 0x14015000 0 0x1000>; 163 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 164 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 165 clocks = <&mmsys CLK_MM_DISP_AAL>; 166}; 167 168gamma@14016000 { 169 compatible = "mediatek,mt8173-disp-gamma"; 170 reg = <0 0x14016000 0 0x1000>; 171 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 172 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 173 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 174}; 175 176ufoe@1401a000 { 177 compatible = "mediatek,mt8173-disp-ufoe"; 178 reg = <0 0x1401a000 0 0x1000>; 179 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 180 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 181 clocks = <&mmsys CLK_MM_DISP_UFOE>; 182}; 183 184dsi0: dsi@1401b000 { 185 /* See mediatek,dsi.txt for details */ 186}; 187 188dpi0: dpi@1401d000 { 189 /* See mediatek,dpi.txt for details */ 190}; 191 192mutex: mutex@14020000 { 193 compatible = "mediatek,mt8173-disp-mutex"; 194 reg = <0 0x14020000 0 0x1000>; 195 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 196 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 197 clocks = <&mmsys CLK_MM_MUTEX_32K>; 198}; 199 200od@14023000 { 201 compatible = "mediatek,mt8173-disp-od"; 202 reg = <0 0x14023000 0 0x1000>; 203 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 204 clocks = <&mmsys CLK_MM_DISP_OD>; 205}; 206