1Mediatek DSI Device 2=================== 3 4The Mediatek DSI function block is a sink of the display subsystem and can 5drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- 6channel output. 7 8Required properties: 9- compatible: "mediatek,<chip>-dsi" 10 the supported chips are mt2701 and mt8173. 11- reg: Physical base address and length of the controller's registers 12- interrupts: The interrupt signal from the function block. 13- clocks: device clocks 14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 15- clock-names: must contain "engine", "digital", and "hs" 16- phys: phandle link to the MIPI D-PHY controller. 17- phy-names: must contain "dphy" 18- port: Output port node with endpoint definitions as described in 19 Documentation/devicetree/bindings/graph.txt. This port should be connected 20 to the input port of an attached DSI panel or DSI-to-eDP encoder chip. 21 22MIPI TX Configuration Module 23============================ 24 25The MIPI TX configuration module controls the MIPI D-PHY. 26 27Required properties: 28- compatible: "mediatek,<chip>-mipi-tx" 29 the supported chips are mt2701 and mt8173. 30- reg: Physical base address and length of the controller's registers 31- clocks: PLL reference clock 32- clock-output-names: name of the output clock line to the DSI encoder 33- #clock-cells: must be <0>; 34- #phy-cells: must be <0>. 35 36Example: 37 38mipi_tx0: mipi-dphy@10215000 { 39 compatible = "mediatek,mt8173-mipi-tx"; 40 reg = <0 0x10215000 0 0x1000>; 41 clocks = <&clk26m>; 42 clock-output-names = "mipi_tx0_pll"; 43 #clock-cells = <0>; 44 #phy-cells = <0>; 45}; 46 47dsi0: dsi@1401b000 { 48 compatible = "mediatek,mt8173-dsi"; 49 reg = <0 0x1401b000 0 0x1000>; 50 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 51 clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, 52 <&mipi_tx0>; 53 clock-names = "engine", "digital", "hs"; 54 phys = <&mipi_tx0>; 55 phy-names = "dphy"; 56 57 port { 58 dsi0_out: endpoint { 59 remote-endpoint = <&panel_in>; 60 }; 61 }; 62}; 63