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1MediaTek Frame Engine Ethernet controller
2=========================================
3
4The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
5have dual GMAC each represented by a child node..
6
7* Ethernet controller node
8
9Required properties:
10- compatible: Should be
11		"mediatek,mt2701-eth": for MT2701 SoC
12		"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13		"mediatek,mt7622-eth": for MT7622 SoC
14- reg: Address and length of the register set for the device
15- interrupts: Should contain the three frame engines interrupts in numeric
16	order. These are fe_int0, fe_int1 and fe_int2.
17- clocks: the clock used by the core
18- clock-names: the names of the clock listed in the clocks property. These are
19	"ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
20        "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
21	"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
22- power-domains: phandle to the power domain that the ethernet is part of
23- resets: Should contain phandles to the ethsys reset signals
24- reset-names: Should contain the names of reset signal listed in the resets
25		property
26		These are "fe", "gmac" and "ppe"
27- mediatek,ethsys: phandle to the syscon node that handles the port setup
28- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
29	which is required for those SoCs equipped with SGMII such as MT7622 SoC.
30- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
31	and driver current: only for MT2701 and MT7623 SoC
32
33* Ethernet MAC node
34
35Required properties:
36- compatible: Should be "mediatek,eth-mac"
37- reg: The number of the MAC
38- phy-handle: see ethernet.txt file in the same directory and
39	the phy-mode "trgmii" required being provided when reg
40	is equal to 0 and the MAC uses fixed-link to connect
41	with internal switch such as MT7530.
42
43Example:
44
45eth: ethernet@1b100000 {
46	compatible = "mediatek,mt7623-eth";
47	reg = <0 0x1b100000 0 0x20000>;
48	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
49		 <&ethsys CLK_ETHSYS_ESW>,
50		 <&ethsys CLK_ETHSYS_GP2>,
51		 <&ethsys CLK_ETHSYS_GP1>;
52	clock-names = "ethif", "esw", "gp2", "gp1";
53	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
54		      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
55		      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
56	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
57	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
58	reset-names = "eth";
59	mediatek,ethsys = <&ethsys>;
60	mediatek,pctl = <&syscfg_pctl_a>;
61	#address-cells = <1>;
62	#size-cells = <0>;
63
64	gmac1: mac@0 {
65		compatible = "mediatek,eth-mac";
66		reg = <0>;
67		phy-handle = <&phy0>;
68	};
69
70	gmac2: mac@1 {
71		compatible = "mediatek,eth-mac";
72		reg = <1>;
73		phy-handle = <&phy1>;
74	};
75
76	mdio-bus {
77		phy0: ethernet-phy@0 {
78			reg = <0>;
79			phy-mode = "rgmii";
80		};
81
82		phy1: ethernet-phy@1 {
83			reg = <1>;
84			phy-mode = "rgmii";
85		};
86	};
87};
88