1* Rockchip Pinmux Controller 2 3The Rockchip Pinmux Controller, enables the IC 4to share one PAD to several functional blocks. The sharing is done by 5multiplexing the PAD input/output signals. For each PAD there are several 6muxing options with option 0 being the use as a GPIO. 7 8Please refer to pinctrl-bindings.txt in this directory for details of the 9common pinctrl bindings used by client devices, including the meaning of the 10phrase "pin configuration node". 11 12The Rockchip pin configuration node is a node of a group of pins which can be 13used for a specific device or function. This node represents both mux and 14config of the pins in that group. The 'pins' selects the function mode(also 15named pin mode) this pin can work on and the 'config' configures various pad 16settings such as pull-up, etc. 17 18The pins are grouped into up to 5 individual pin banks which need to be 19defined as gpio sub-nodes of the pinmux controller. 20 21Required properties for iomux controller: 22 - compatible: should be 23 "rockchip,px30-pinctrl": for Rockchip PX30 24 "rockchip,rv1108-pinctrl": for Rockchip RV1108 25 "rockchip,rk2928-pinctrl": for Rockchip RK2928 26 "rockchip,rk3066a-pinctrl": for Rockchip RK3066a 27 "rockchip,rk3066b-pinctrl": for Rockchip RK3066b 28 "rockchip,rk3128-pinctrl": for Rockchip RK3128 29 "rockchip,rk3188-pinctrl": for Rockchip RK3188 30 "rockchip,rk3228-pinctrl": for Rockchip RK3228 31 "rockchip,rk3288-pinctrl": for Rockchip RK3288 32 "rockchip,rk3328-pinctrl": for Rockchip RK3328 33 "rockchip,rk3368-pinctrl": for Rockchip RK3368 34 "rockchip,rk3399-pinctrl": for Rockchip RK3399 35 36 - rockchip,grf: phandle referencing a syscon providing the 37 "general register files" 38 39Optional properties for iomux controller: 40 - rockchip,pmu: phandle referencing a syscon providing the pmu registers 41 as some SoCs carry parts of the iomux controller registers there. 42 Required for at least rk3188 and rk3288. On the rk3368 this should 43 point to the PMUGRF syscon. 44 45Deprecated properties for iomux controller: 46 - reg: first element is the general register space of the iomux controller 47 It should be large enough to contain also separate pull registers. 48 second element is the separate pull register space of the rk3188. 49 Use rockchip,grf and rockchip,pmu described above instead. 50 51Required properties for gpio sub nodes: 52 - compatible: "rockchip,gpio-bank" 53 - reg: register of the gpio bank (different than the iomux registerset) 54 - interrupts: base interrupt of the gpio bank in the interrupt controller 55 - clocks: clock that drives this bank 56 - gpio-controller: identifies the node as a gpio controller and pin bank. 57 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 58 binding is used, the amount of cells must be specified as 2. See generic 59 GPIO binding documentation for description of particular cells. 60 - interrupt-controller: identifies the controller node as interrupt-parent. 61 - #interrupt-cells: the value of this property should be 2 and the interrupt 62 cells should use the standard two-cell scheme described in 63 bindings/interrupt-controller/interrupts.txt 64 65Deprecated properties for gpio sub nodes: 66 - compatible: "rockchip,rk3188-gpio-bank0" 67 - reg: second element: separate pull register for rk3188 bank0, use 68 rockchip,pmu described above instead 69 70Required properties for pin configuration node: 71 - rockchip,pins: 3 integers array, represents a group of pins mux and config 72 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. 73 The MUX 0 means gpio and MUX 1 to N mean the specific device function. 74 The phandle of a node containing the generic pinconfig options 75 to use, as described in pinctrl-bindings.txt in this directory. 76 77Examples: 78 79#include <dt-bindings/pinctrl/rockchip.h> 80 81... 82 83pinctrl@20008000 { 84 compatible = "rockchip,rk3066a-pinctrl"; 85 rockchip,grf = <&grf>; 86 87 #address-cells = <1>; 88 #size-cells = <1>; 89 ranges; 90 91 gpio0: gpio0@20034000 { 92 compatible = "rockchip,gpio-bank"; 93 reg = <0x20034000 0x100>; 94 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&clk_gates8 9>; 96 97 gpio-controller; 98 #gpio-cells = <2>; 99 100 interrupt-controller; 101 #interrupt-cells = <2>; 102 }; 103 104 ... 105 106 pcfg_pull_default: pcfg_pull_default { 107 bias-pull-pin-default 108 }; 109 110 uart2 { 111 uart2_xfer: uart2-xfer { 112 rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, 113 <RK_GPIO1 9 1 &pcfg_pull_default>; 114 }; 115 }; 116}; 117 118uart2: serial@20064000 { 119 compatible = "snps,dw-apb-uart"; 120 reg = <0x20064000 0x400>; 121 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 122 reg-shift = <2>; 123 reg-io-width = <1>; 124 clocks = <&mux_uart2>; 125 126 pinctrl-names = "default"; 127 pinctrl-0 = <&uart2_xfer>; 128}; 129 130Example for rk3188: 131 132 pinctrl@20008000 { 133 compatible = "rockchip,rk3188-pinctrl"; 134 rockchip,grf = <&grf>; 135 rockchip,pmu = <&pmu>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges; 139 140 gpio0: gpio0@2000a000 { 141 compatible = "rockchip,rk3188-gpio-bank0"; 142 reg = <0x2000a000 0x100>; 143 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clk_gates8 9>; 145 146 gpio-controller; 147 #gpio-cells = <2>; 148 149 interrupt-controller; 150 #interrupt-cells = <2>; 151 }; 152 153 gpio1: gpio1@2003c000 { 154 compatible = "rockchip,gpio-bank"; 155 reg = <0x2003c000 0x100>; 156 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&clk_gates8 10>; 158 159 gpio-controller; 160 #gpio-cells = <2>; 161 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 }; 165 166 ... 167 168 }; 169