1* STM32 GPIO and Pin Mux/Config controller 2 3STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware 4controller. It controls the input/output settings on the available pins and 5also provides ability to multiplex and configure the output of various on-chip 6controllers onto these pads. 7 8Pin controller node: 9Required properies: 10 - compatible: value should be one of the following: 11 "st,stm32f429-pinctrl" 12 "st,stm32f469-pinctrl" 13 "st,stm32f746-pinctrl" 14 "st,stm32f769-pinctrl" 15 "st,stm32h743-pinctrl" 16 "st,stm32mp157-pinctrl" 17 "st,stm32mp157-z-pinctrl" 18 - #address-cells: The value of this property must be 1 19 - #size-cells : The value of this property must be 1 20 - ranges : defines mapping between pin controller node (parent) to 21 gpio-bank node (children). 22 - pins-are-numbered: Specify the subnodes are using numbered pinmux to 23 specify pins. 24 25GPIO controller/bank node: 26Required properties: 27 - gpio-controller : Indicates this device is a GPIO controller 28 - #gpio-cells : Should be two. 29 The first cell is the pin number 30 The second one is the polarity: 31 - 0 for active high 32 - 1 for active low 33 - reg : The gpio address range, relative to the pinctrl range 34 - clocks : clock that drives this bank 35 - st,bank-name : Should be a name string for this bank as specified in 36 the datasheet 37 38Optional properties: 39 - reset: : Reference to the reset controller 40 - st,syscfg: Should be phandle/offset/mask. 41 -The phandle to the syscon node which includes IRQ mux selection register. 42 -The offset of the IRQ mux selection register 43 -The field mask of IRQ mux, needed if different of 0xf. 44 - gpio-ranges: Define a dedicated mapping between a pin-controller and 45 a gpio controller. Format is <&phandle a b c> with: 46 -(phandle): phandle of pin-controller. 47 -(a): gpio base offset in range. 48 -(b): pin base offset in range. 49 -(c): gpio count in range 50 This entry has to be used either if there are holes inside a bank: 51 GPIOB0/B1/B2/B14/B15 (see example 2) 52 or if banks are not contiguous: 53 GPIOA/B/C/E... 54 NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller 55 have to use a "gpio-ranges" entry. 56 More details in Documentation/devicetree/bindings/gpio/gpio.txt. 57 - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line 58 used to select GPIOs as interrupts). 59 60Example 1: 61#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> 62... 63 64 pin-controller { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "st,stm32f429-pinctrl"; 68 ranges = <0 0x40020000 0x3000>; 69 pins-are-numbered; 70 71 gpioa: gpio@40020000 { 72 gpio-controller; 73 #gpio-cells = <2>; 74 reg = <0x0 0x400>; 75 resets = <&reset_ahb1 0>; 76 st,bank-name = "GPIOA"; 77 }; 78 ... 79 pin-functions nodes follow... 80 }; 81 82Example 2: 83#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> 84... 85 86 pinctrl: pin-controller { 87 #address-cells = <1>; 88 #size-cells = <1>; 89 compatible = "st,stm32f429-pinctrl"; 90 ranges = <0 0x40020000 0x3000>; 91 pins-are-numbered; 92 93 gpioa: gpio@40020000 { 94 gpio-controller; 95 #gpio-cells = <2>; 96 reg = <0x0 0x400>; 97 resets = <&reset_ahb1 0>; 98 st,bank-name = "GPIOA"; 99 gpio-ranges = <&pinctrl 0 0 16>; 100 }; 101 102 gpiob: gpio@40020400 { 103 gpio-controller; 104 #gpio-cells = <2>; 105 reg = <0x0 0x400>; 106 resets = <&reset_ahb1 0>; 107 st,bank-name = "GPIOB"; 108 ngpios = 4; 109 gpio-ranges = <&pinctrl 0 16 3>, 110 <&pinctrl 14 30 2>; 111 }; 112 113 114 ... 115 pin-functions nodes follow... 116 }; 117 118 119Contents of function subnode node: 120---------------------------------- 121Subnode format 122A pinctrl node should contain at least one subnode representing the 123pinctrl group available on the machine. Each subnode will list the 124pins it needs, and how they should be configured, with regard to muxer 125configuration, pullups, drive, output high/low and output speed. 126 127 node { 128 pinmux = <PIN_NUMBER_PINMUX>; 129 GENERIC_PINCONFIG; 130 }; 131 132Required properties: 133- pinmux: integer array, represents gpio pin number and mux setting. 134 Supported pin number and mux varies for different SoCs, and are defined in 135 dt-bindings/pinctrl/<soc>-pinfunc.h directly. 136 These defines are calculated as: 137 ((port * 16 + line) << 8) | function 138 With: 139 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) 140 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) 141 - function: The function number, can be: 142 * 0 : GPIO 143 * 1 : Alternate Function 0 144 * 2 : Alternate Function 1 145 * 3 : Alternate Function 2 146 * ... 147 * 16 : Alternate Function 15 148 * 17 : Analog 149 150 To simplify the usage, macro is available to generate "pinmux" field. 151 This macro is available here: 152 - include/dt-bindings/pinctrl/stm32-pinfunc.h 153 154 Some examples of using macro: 155 /* GPIO A9 set as alernate function 2 */ 156 ... { 157 pinmux = <STM32_PINMUX('A', 9, AF2)>; 158 }; 159 /* GPIO A9 set as GPIO */ 160 ... { 161 pinmux = <STM32_PINMUX('A', 9, GPIO)>; 162 }; 163 /* GPIO A9 set as analog */ 164 ... { 165 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; 166 }; 167 168Optional properties: 169- GENERIC_PINCONFIG: is the generic pinconfig options to use. 170 Available options are: 171 - bias-disable, 172 - bias-pull-down, 173 - bias-pull-up, 174 - drive-push-pull, 175 - drive-open-drain, 176 - output-low 177 - output-high 178 - slew-rate = <x>, with x being: 179 < 0 > : Low speed 180 < 1 > : Medium speed 181 < 2 > : Fast speed 182 < 3 > : High speed 183 184Example: 185 186pin-controller { 187... 188 usart1_pins_a: usart1@0 { 189 pins1 { 190 pinmux = <STM32_PINMUX('A', 9, AF7)>; 191 bias-disable; 192 drive-push-pull; 193 slew-rate = <0>; 194 }; 195 pins2 { 196 pinmux = <STM32_PINMUX('A', 10, AF7)>; 197 bias-disable; 198 }; 199 }; 200}; 201 202&usart1 { 203 pinctrl-0 = <&usart1_pins_a>; 204 pinctrl-names = "default"; 205}; 206