1MediaTek PWM controller 2 3Required properties: 4 - compatible: should be "mediatek,<name>-pwm": 5 - "mediatek,mt2712-pwm": found on mt2712 SoC. 6 - "mediatek,mt7622-pwm": found on mt7622 SoC. 7 - "mediatek,mt7623-pwm": found on mt7623 SoC. 8 - "mediatek,mt7628-pwm": found on mt7628 SoC. 9 - reg: physical base address and length of the controller's registers. 10 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of 11 the cell format. 12 - clocks: phandle and clock specifier of the PWM reference clock. 13 - clock-names: must contain the following, except for MT7628 which 14 has no clocks 15 - "top": the top clock generator 16 - "main": clock used by the PWM core 17 - "pwm1-8": the eight per PWM clocks for mt2712 18 - "pwm1-6": the six per PWM clocks for mt7622 19 - "pwm1-5": the five per PWM clocks for mt7623 20 - pinctrl-names: Must contain a "default" entry. 21 - pinctrl-0: One property must exist for each entry in pinctrl-names. 22 See pinctrl/pinctrl-bindings.txt for details of the property values. 23 24Example: 25 pwm0: pwm@11006000 { 26 compatible = "mediatek,mt7623-pwm"; 27 reg = <0 0x11006000 0 0x1000>; 28 #pwm-cells = <2>; 29 clocks = <&topckgen CLK_TOP_PWM_SEL>, 30 <&pericfg CLK_PERI_PWM>, 31 <&pericfg CLK_PERI_PWM1>, 32 <&pericfg CLK_PERI_PWM2>, 33 <&pericfg CLK_PERI_PWM3>, 34 <&pericfg CLK_PERI_PWM4>, 35 <&pericfg CLK_PERI_PWM5>; 36 clock-names = "top", "main", "pwm1", "pwm2", 37 "pwm3", "pwm4", "pwm5"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pwm0_pins>; 40 }; 41