1/* 2 * Copyright 2016 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49 50/ { 51 /* these are used by bootloader for disabling nodes */ 52 aliases { 53 led0 = &led0; 54 led1 = &led1; 55 nand = &gpmi; 56 usb0 = &usbh1; 57 usb1 = &usbotg; 58 }; 59 60 chosen { 61 stdout-path = &uart2; 62 }; 63 64 leds { 65 compatible = "gpio-leds"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_gpio_leds>; 68 69 led0: user1 { 70 label = "user1"; 71 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 72 default-state = "on"; 73 linux,default-trigger = "heartbeat"; 74 }; 75 76 led1: user2 { 77 label = "user2"; 78 gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 79 default-state = "off"; 80 }; 81 }; 82 83 memory@10000000 { 84 reg = <0x10000000 0x20000000>; 85 }; 86 87 pps { 88 compatible = "pps-gpio"; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_pps>; 91 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 92 status = "okay"; 93 }; 94 95 reg_5p0v: regulator-5p0v { 96 compatible = "regulator-fixed"; 97 regulator-name = "5P0V"; 98 regulator-min-microvolt = <5000000>; 99 regulator-max-microvolt = <5000000>; 100 regulator-always-on; 101 }; 102 103 reg_usb_otg_vbus: regulator-usb-otg-vbus { 104 compatible = "regulator-fixed"; 105 regulator-name = "usb_otg_vbus"; 106 regulator-min-microvolt = <5000000>; 107 regulator-max-microvolt = <5000000>; 108 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 109 enable-active-high; 110 }; 111}; 112 113&gpmi { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_gpmi_nand>; 116 status = "okay"; 117}; 118 119&hdmi { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_hdmi>; 122 ddc-i2c-bus = <&i2c3>; 123 status = "okay"; 124}; 125 126&i2c1 { 127 clock-frequency = <100000>; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_i2c1>; 130 status = "okay"; 131 132 gpio: pca9555@23 { 133 compatible = "nxp,pca9555"; 134 reg = <0x23>; 135 gpio-controller; 136 #gpio-cells = <2>; 137 }; 138 139 eeprom1: eeprom@50 { 140 compatible = "atmel,24c02"; 141 reg = <0x50>; 142 pagesize = <16>; 143 }; 144 145 eeprom2: eeprom@51 { 146 compatible = "atmel,24c02"; 147 reg = <0x51>; 148 pagesize = <16>; 149 }; 150 151 eeprom3: eeprom@52 { 152 compatible = "atmel,24c02"; 153 reg = <0x52>; 154 pagesize = <16>; 155 }; 156 157 eeprom4: eeprom@53 { 158 compatible = "atmel,24c02"; 159 reg = <0x53>; 160 pagesize = <16>; 161 }; 162 163 rtc: ds1672@68 { 164 compatible = "dallas,ds1672"; 165 reg = <0x68>; 166 }; 167}; 168 169&i2c2 { 170 clock-frequency = <100000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_i2c2>; 173 status = "okay"; 174 175 ltc3676: pmic@3c { 176 compatible = "lltc,ltc3676"; 177 reg = <0x3c>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_pmic>; 180 interrupt-parent = <&gpio1>; 181 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 182 183 regulators { 184 /* VDD_SOC (1+R1/R2 = 1.635) */ 185 reg_vdd_soc: sw1 { 186 regulator-name = "vddsoc"; 187 regulator-min-microvolt = <674400>; 188 regulator-max-microvolt = <1308000>; 189 lltc,fb-voltage-divider = <127000 200000>; 190 regulator-ramp-delay = <7000>; 191 regulator-boot-on; 192 regulator-always-on; 193 }; 194 195 /* VDD_DDR (1+R1/R2 = 2.105) */ 196 reg_vdd_ddr: sw2 { 197 regulator-name = "vddddr"; 198 regulator-min-microvolt = <868310>; 199 regulator-max-microvolt = <1684000>; 200 lltc,fb-voltage-divider = <221000 200000>; 201 regulator-ramp-delay = <7000>; 202 regulator-boot-on; 203 regulator-always-on; 204 }; 205 206 /* VDD_ARM (1+R1/R2 = 1.635) */ 207 reg_vdd_arm: sw3 { 208 regulator-name = "vddarm"; 209 regulator-min-microvolt = <674400>; 210 regulator-max-microvolt = <1308000>; 211 lltc,fb-voltage-divider = <127000 200000>; 212 regulator-ramp-delay = <7000>; 213 regulator-boot-on; 214 regulator-always-on; 215 }; 216 217 /* VDD_3P3 (1+R1/R2 = 1.281) */ 218 reg_3p3v: sw4 { 219 regulator-name = "vdd3p3"; 220 regulator-min-microvolt = <1880000>; 221 regulator-max-microvolt = <3647000>; 222 lltc,fb-voltage-divider = <200000 56200>; 223 regulator-ramp-delay = <7000>; 224 regulator-boot-on; 225 regulator-always-on; 226 }; 227 228 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ 229 reg_1p8a: ldo2 { 230 regulator-name = "vdd1p8a"; 231 regulator-min-microvolt = <1816125>; 232 regulator-max-microvolt = <1816125>; 233 lltc,fb-voltage-divider = <301000 200000>; 234 regulator-boot-on; 235 regulator-always-on; 236 }; 237 238 /* VDD_1P8b: microSD VDD_1P8 */ 239 reg_1p8b: ldo3 { 240 regulator-name = "vdd1p8b"; 241 regulator-min-microvolt = <1800000>; 242 regulator-max-microvolt = <1800000>; 243 regulator-boot-on; 244 }; 245 246 /* VDD_HIGH (1+R1/R2 = 4.17) */ 247 reg_3p0v: ldo4 { 248 regulator-name = "vdd3p0"; 249 regulator-min-microvolt = <3023250>; 250 regulator-max-microvolt = <3023250>; 251 lltc,fb-voltage-divider = <634000 200000>; 252 regulator-boot-on; 253 regulator-always-on; 254 }; 255 }; 256 }; 257}; 258 259&i2c3 { 260 clock-frequency = <100000>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_i2c3>; 263 status = "okay"; 264 265 adv7180: camera@20 { 266 compatible = "adi,adv7180"; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_adv7180>; 269 reg = <0x20>; 270 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 271 interrupt-parent = <&gpio5>; 272 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 273 274 port { 275 adv7180_to_ipu1_csi0_mux: endpoint { 276 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 277 bus-width = <8>; 278 }; 279 }; 280 }; 281}; 282 283&ipu1_csi0_from_ipu1_csi0_mux { 284 bus-width = <8>; 285}; 286 287&ipu1_csi0_mux_from_parallel_sensor { 288 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 289 bus-width = <8>; 290}; 291 292&ipu1_csi0 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_ipu1_csi0>; 295}; 296 297&pcie { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_pcie>; 300 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 301 status = "okay"; 302}; 303 304&pwm2 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 307 status = "disabled"; 308}; 309 310&pwm3 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 313 status = "disabled"; 314}; 315 316&pwm4 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 319 status = "disabled"; 320}; 321 322&uart2 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_uart2>; 325 status = "okay"; 326}; 327 328&uart3 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart3>; 331 status = "okay"; 332}; 333 334&uart4 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_uart4>; 337 status = "okay"; 338}; 339 340&uart5 { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_uart5>; 343 status = "okay"; 344}; 345 346&usbh1 { 347 status = "okay"; 348}; 349 350&usbotg { 351 vbus-supply = <®_usb_otg_vbus>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_usbotg>; 354 disable-over-current; 355 status = "okay"; 356}; 357 358&usdhc3 { 359 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 360 pinctrl-0 = <&pinctrl_usdhc3>; 361 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 362 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 363 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 364 status = "okay"; 365}; 366 367&wdog1 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_wdog>; 370 fsl,ext-reset-output; 371}; 372 373&iomuxc { 374 pinctrl_adv7180: adv7180grp { 375 fsl,pins = < 376 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 377 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 378 >; 379 }; 380 381 pinctrl_gpmi_nand: gpminandgrp { 382 fsl,pins = < 383 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 384 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 385 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 386 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 387 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 388 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 389 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 390 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 391 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 392 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 393 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 394 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 395 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 396 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 397 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 398 >; 399 }; 400 401 pinctrl_hdmi: hdmigrp { 402 fsl,pins = < 403 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 404 >; 405 }; 406 407 pinctrl_i2c1: i2c1grp { 408 fsl,pins = < 409 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 410 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 411 >; 412 }; 413 414 pinctrl_i2c2: i2c2grp { 415 fsl,pins = < 416 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 417 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 418 >; 419 }; 420 421 pinctrl_i2c3: i2c3grp { 422 fsl,pins = < 423 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 424 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 425 >; 426 }; 427 428 pinctrl_ipu1_csi0: ipu1csi0grp { 429 fsl,pins = < 430 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 431 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 432 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 433 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 434 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 435 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 436 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 437 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 438 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 439 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 440 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 441 >; 442 }; 443 444 pinctrl_gpio_leds: gpioledsgrp { 445 fsl,pins = < 446 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 447 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 448 >; 449 }; 450 451 pinctrl_pcie: pciegrp { 452 fsl,pins = < 453 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 454 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 455 >; 456 }; 457 458 pinctrl_pmic: pmicgrp { 459 fsl,pins = < 460 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 461 >; 462 }; 463 464 pinctrl_pps: ppsgrp { 465 fsl,pins = < 466 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 467 >; 468 }; 469 470 pinctrl_pwm2: pwm2grp { 471 fsl,pins = < 472 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 473 >; 474 }; 475 476 pinctrl_pwm3: pwm3grp { 477 fsl,pins = < 478 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 479 >; 480 }; 481 482 pinctrl_pwm4: pwm4grp { 483 fsl,pins = < 484 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 485 >; 486 }; 487 488 pinctrl_uart2: uart2grp { 489 fsl,pins = < 490 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 491 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 492 >; 493 }; 494 495 pinctrl_uart3: uart3grp { 496 fsl,pins = < 497 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 498 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 499 >; 500 }; 501 502 pinctrl_uart4: uart4grp { 503 fsl,pins = < 504 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 505 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 506 >; 507 }; 508 509 pinctrl_uart5: uart5grp { 510 fsl,pins = < 511 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 512 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 513 >; 514 }; 515 516 pinctrl_usbotg: usbotggrp { 517 fsl,pins = < 518 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 519 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 520 >; 521 }; 522 523 pinctrl_usdhc3: usdhc3grp { 524 fsl,pins = < 525 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 526 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 527 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 528 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 529 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 530 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 531 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 532 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 533 >; 534 }; 535 536 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 537 fsl,pins = < 538 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 539 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 540 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 541 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 542 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 543 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 544 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 545 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 546 >; 547 }; 548 549 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 550 fsl,pins = < 551 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 552 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 553 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 554 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 555 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 556 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 557 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 558 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 559 >; 560 }; 561 562 pinctrl_wdog: wdoggrp { 563 fsl,pins = < 564 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 565 >; 566 }; 567}; 568