1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 clocks = <&cru ARMCLKL>; 75 #cooling-cells = <2>; /* min followed by max */ 76 dynamic-power-coefficient = <100>; 77 }; 78 79 cpu_l1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 reg = <0x0 0x1>; 83 enable-method = "psci"; 84 clocks = <&cru ARMCLKL>; 85 #cooling-cells = <2>; /* min followed by max */ 86 dynamic-power-coefficient = <100>; 87 }; 88 89 cpu_l2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53", "arm,armv8"; 92 reg = <0x0 0x2>; 93 enable-method = "psci"; 94 clocks = <&cru ARMCLKL>; 95 #cooling-cells = <2>; /* min followed by max */ 96 dynamic-power-coefficient = <100>; 97 }; 98 99 cpu_l3: cpu@3 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53", "arm,armv8"; 102 reg = <0x0 0x3>; 103 enable-method = "psci"; 104 clocks = <&cru ARMCLKL>; 105 #cooling-cells = <2>; /* min followed by max */ 106 dynamic-power-coefficient = <100>; 107 }; 108 109 cpu_b0: cpu@100 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a72", "arm,armv8"; 112 reg = <0x0 0x100>; 113 enable-method = "psci"; 114 clocks = <&cru ARMCLKB>; 115 #cooling-cells = <2>; /* min followed by max */ 116 dynamic-power-coefficient = <436>; 117 }; 118 119 cpu_b1: cpu@101 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a72", "arm,armv8"; 122 reg = <0x0 0x101>; 123 enable-method = "psci"; 124 clocks = <&cru ARMCLKB>; 125 #cooling-cells = <2>; /* min followed by max */ 126 dynamic-power-coefficient = <436>; 127 }; 128 }; 129 130 display-subsystem { 131 compatible = "rockchip,display-subsystem"; 132 ports = <&vopl_out>, <&vopb_out>; 133 }; 134 135 pmu_a53 { 136 compatible = "arm,cortex-a53-pmu"; 137 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 138 }; 139 140 pmu_a72 { 141 compatible = "arm,cortex-a72-pmu"; 142 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 153 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 154 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 155 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 156 arm,no-tick-in-suspend; 157 }; 158 159 xin24m: xin24m { 160 compatible = "fixed-clock"; 161 clock-frequency = <24000000>; 162 clock-output-names = "xin24m"; 163 #clock-cells = <0>; 164 }; 165 166 amba { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 dmac_bus: dma-controller@ff6d0000 { 173 compatible = "arm,pl330", "arm,primecell"; 174 reg = <0x0 0xff6d0000 0x0 0x4000>; 175 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 176 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 177 #dma-cells = <1>; 178 clocks = <&cru ACLK_DMAC0_PERILP>; 179 clock-names = "apb_pclk"; 180 }; 181 182 dmac_peri: dma-controller@ff6e0000 { 183 compatible = "arm,pl330", "arm,primecell"; 184 reg = <0x0 0xff6e0000 0x0 0x4000>; 185 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 187 #dma-cells = <1>; 188 clocks = <&cru ACLK_DMAC1_PERILP>; 189 clock-names = "apb_pclk"; 190 }; 191 }; 192 193 pcie0: pcie@f8000000 { 194 compatible = "rockchip,rk3399-pcie"; 195 reg = <0x0 0xf8000000 0x0 0x2000000>, 196 <0x0 0xfd000000 0x0 0x1000000>; 197 reg-names = "axi-base", "apb-base"; 198 #address-cells = <3>; 199 #size-cells = <2>; 200 #interrupt-cells = <1>; 201 aspm-no-l0s; 202 bus-range = <0x0 0x1f>; 203 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 204 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 205 clock-names = "aclk", "aclk-perf", 206 "hclk", "pm"; 207 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 208 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 209 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 210 interrupt-names = "sys", "legacy", "client"; 211 interrupt-map-mask = <0 0 0 7>; 212 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 213 <0 0 0 2 &pcie0_intc 1>, 214 <0 0 0 3 &pcie0_intc 2>, 215 <0 0 0 4 &pcie0_intc 3>; 216 linux,pci-domain = <0>; 217 max-link-speed = <1>; 218 msi-map = <0x0 &its 0x0 0x1000>; 219 phys = <&pcie_phy 0>, <&pcie_phy 1>, 220 <&pcie_phy 2>, <&pcie_phy 3>; 221 phy-names = "pcie-phy-0", "pcie-phy-1", 222 "pcie-phy-2", "pcie-phy-3"; 223 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 224 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 225 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 226 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 227 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 228 <&cru SRST_A_PCIE>; 229 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 230 "pm", "pclk", "aclk"; 231 status = "disabled"; 232 233 pcie0_intc: interrupt-controller { 234 interrupt-controller; 235 #address-cells = <0>; 236 #interrupt-cells = <1>; 237 }; 238 }; 239 240 gmac: ethernet@fe300000 { 241 compatible = "rockchip,rk3399-gmac"; 242 reg = <0x0 0xfe300000 0x0 0x10000>; 243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 244 interrupt-names = "macirq"; 245 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 246 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 247 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 248 <&cru PCLK_GMAC>; 249 clock-names = "stmmaceth", "mac_clk_rx", 250 "mac_clk_tx", "clk_mac_ref", 251 "clk_mac_refout", "aclk_mac", 252 "pclk_mac"; 253 power-domains = <&power RK3399_PD_GMAC>; 254 resets = <&cru SRST_A_GMAC>; 255 reset-names = "stmmaceth"; 256 rockchip,grf = <&grf>; 257 status = "disabled"; 258 }; 259 260 sdio0: dwmmc@fe310000 { 261 compatible = "rockchip,rk3399-dw-mshc", 262 "rockchip,rk3288-dw-mshc"; 263 reg = <0x0 0xfe310000 0x0 0x4000>; 264 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 265 max-frequency = <150000000>; 266 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 267 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 269 fifo-depth = <0x100>; 270 power-domains = <&power RK3399_PD_SDIOAUDIO>; 271 resets = <&cru SRST_SDIO0>; 272 reset-names = "reset"; 273 status = "disabled"; 274 }; 275 276 sdmmc: dwmmc@fe320000 { 277 compatible = "rockchip,rk3399-dw-mshc", 278 "rockchip,rk3288-dw-mshc"; 279 reg = <0x0 0xfe320000 0x0 0x4000>; 280 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 281 max-frequency = <150000000>; 282 assigned-clocks = <&cru HCLK_SD>; 283 assigned-clock-rates = <200000000>; 284 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 285 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 287 fifo-depth = <0x100>; 288 power-domains = <&power RK3399_PD_SD>; 289 resets = <&cru SRST_SDMMC>; 290 reset-names = "reset"; 291 status = "disabled"; 292 }; 293 294 sdhci: sdhci@fe330000 { 295 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 296 reg = <0x0 0xfe330000 0x0 0x10000>; 297 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 298 arasan,soc-ctl-syscon = <&grf>; 299 assigned-clocks = <&cru SCLK_EMMC>; 300 assigned-clock-rates = <200000000>; 301 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 302 clock-names = "clk_xin", "clk_ahb"; 303 clock-output-names = "emmc_cardclock"; 304 #clock-cells = <0>; 305 phys = <&emmc_phy>; 306 phy-names = "phy_arasan"; 307 power-domains = <&power RK3399_PD_EMMC>; 308 disable-cqe-dcmd; 309 status = "disabled"; 310 }; 311 312 usb_host0_ehci: usb@fe380000 { 313 compatible = "generic-ehci"; 314 reg = <0x0 0xfe380000 0x0 0x20000>; 315 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 316 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 317 <&u2phy0>; 318 clock-names = "usbhost", "arbiter", 319 "utmi"; 320 phys = <&u2phy0_host>; 321 phy-names = "usb"; 322 status = "disabled"; 323 }; 324 325 usb_host0_ohci: usb@fe3a0000 { 326 compatible = "generic-ohci"; 327 reg = <0x0 0xfe3a0000 0x0 0x20000>; 328 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 329 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 330 <&u2phy0>; 331 clock-names = "usbhost", "arbiter", 332 "utmi"; 333 phys = <&u2phy0_host>; 334 phy-names = "usb"; 335 status = "disabled"; 336 }; 337 338 usb_host1_ehci: usb@fe3c0000 { 339 compatible = "generic-ehci"; 340 reg = <0x0 0xfe3c0000 0x0 0x20000>; 341 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 342 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 343 <&u2phy1>; 344 clock-names = "usbhost", "arbiter", 345 "utmi"; 346 phys = <&u2phy1_host>; 347 phy-names = "usb"; 348 status = "disabled"; 349 }; 350 351 usb_host1_ohci: usb@fe3e0000 { 352 compatible = "generic-ohci"; 353 reg = <0x0 0xfe3e0000 0x0 0x20000>; 354 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 355 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 356 <&u2phy1>; 357 clock-names = "usbhost", "arbiter", 358 "utmi"; 359 phys = <&u2phy1_host>; 360 phy-names = "usb"; 361 status = "disabled"; 362 }; 363 364 usbdrd3_0: usb@fe800000 { 365 compatible = "rockchip,rk3399-dwc3"; 366 #address-cells = <2>; 367 #size-cells = <2>; 368 ranges; 369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 372 clock-names = "ref_clk", "suspend_clk", 373 "bus_clk", "aclk_usb3_rksoc_axi_perf", 374 "aclk_usb3", "grf_clk"; 375 resets = <&cru SRST_A_USB3_OTG0>; 376 reset-names = "usb3-otg"; 377 status = "disabled"; 378 379 usbdrd_dwc3_0: usb@fe800000 { 380 compatible = "snps,dwc3"; 381 reg = <0x0 0xfe800000 0x0 0x100000>; 382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 383 dr_mode = "otg"; 384 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 385 phy-names = "usb2-phy", "usb3-phy"; 386 phy_type = "utmi_wide"; 387 snps,dis_enblslpm_quirk; 388 snps,dis-u2-freeclk-exists-quirk; 389 snps,dis_u2_susphy_quirk; 390 snps,dis-del-phy-power-chg-quirk; 391 snps,dis-tx-ipgap-linecheck-quirk; 392 power-domains = <&power RK3399_PD_USB3>; 393 status = "disabled"; 394 }; 395 }; 396 397 usbdrd3_1: usb@fe900000 { 398 compatible = "rockchip,rk3399-dwc3"; 399 #address-cells = <2>; 400 #size-cells = <2>; 401 ranges; 402 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 403 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 404 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 405 clock-names = "ref_clk", "suspend_clk", 406 "bus_clk", "aclk_usb3_rksoc_axi_perf", 407 "aclk_usb3", "grf_clk"; 408 resets = <&cru SRST_A_USB3_OTG1>; 409 reset-names = "usb3-otg"; 410 status = "disabled"; 411 412 usbdrd_dwc3_1: usb@fe900000 { 413 compatible = "snps,dwc3"; 414 reg = <0x0 0xfe900000 0x0 0x100000>; 415 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 416 dr_mode = "otg"; 417 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 418 phy-names = "usb2-phy", "usb3-phy"; 419 phy_type = "utmi_wide"; 420 snps,dis_enblslpm_quirk; 421 snps,dis-u2-freeclk-exists-quirk; 422 snps,dis_u2_susphy_quirk; 423 snps,dis-del-phy-power-chg-quirk; 424 snps,dis-tx-ipgap-linecheck-quirk; 425 power-domains = <&power RK3399_PD_USB3>; 426 status = "disabled"; 427 }; 428 }; 429 430 cdn_dp: dp@fec00000 { 431 compatible = "rockchip,rk3399-cdn-dp"; 432 reg = <0x0 0xfec00000 0x0 0x100000>; 433 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 434 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 435 assigned-clock-rates = <100000000>, <200000000>; 436 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 437 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 438 clock-names = "core-clk", "pclk", "spdif", "grf"; 439 phys = <&tcphy0_dp>, <&tcphy1_dp>; 440 power-domains = <&power RK3399_PD_HDCP>; 441 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 442 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 443 reset-names = "spdif", "dptx", "apb", "core"; 444 rockchip,grf = <&grf>; 445 #sound-dai-cells = <1>; 446 status = "disabled"; 447 448 ports { 449 dp_in: port { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 dp_in_vopb: endpoint@0 { 454 reg = <0>; 455 remote-endpoint = <&vopb_out_dp>; 456 }; 457 458 dp_in_vopl: endpoint@1 { 459 reg = <1>; 460 remote-endpoint = <&vopl_out_dp>; 461 }; 462 }; 463 }; 464 }; 465 466 gic: interrupt-controller@fee00000 { 467 compatible = "arm,gic-v3"; 468 #interrupt-cells = <4>; 469 #address-cells = <2>; 470 #size-cells = <2>; 471 ranges; 472 interrupt-controller; 473 474 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 475 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 476 <0x0 0xfff00000 0 0x10000>, /* GICC */ 477 <0x0 0xfff10000 0 0x10000>, /* GICH */ 478 <0x0 0xfff20000 0 0x10000>; /* GICV */ 479 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 480 its: interrupt-controller@fee20000 { 481 compatible = "arm,gic-v3-its"; 482 msi-controller; 483 reg = <0x0 0xfee20000 0x0 0x20000>; 484 }; 485 486 ppi-partitions { 487 ppi_cluster0: interrupt-partition-0 { 488 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 489 }; 490 491 ppi_cluster1: interrupt-partition-1 { 492 affinity = <&cpu_b0 &cpu_b1>; 493 }; 494 }; 495 }; 496 497 saradc: saradc@ff100000 { 498 compatible = "rockchip,rk3399-saradc"; 499 reg = <0x0 0xff100000 0x0 0x100>; 500 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 501 #io-channel-cells = <1>; 502 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 503 clock-names = "saradc", "apb_pclk"; 504 resets = <&cru SRST_P_SARADC>; 505 reset-names = "saradc-apb"; 506 status = "disabled"; 507 }; 508 509 i2c1: i2c@ff110000 { 510 compatible = "rockchip,rk3399-i2c"; 511 reg = <0x0 0xff110000 0x0 0x1000>; 512 assigned-clocks = <&cru SCLK_I2C1>; 513 assigned-clock-rates = <200000000>; 514 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 515 clock-names = "i2c", "pclk"; 516 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&i2c1_xfer>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 status = "disabled"; 522 }; 523 524 i2c2: i2c@ff120000 { 525 compatible = "rockchip,rk3399-i2c"; 526 reg = <0x0 0xff120000 0x0 0x1000>; 527 assigned-clocks = <&cru SCLK_I2C2>; 528 assigned-clock-rates = <200000000>; 529 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 530 clock-names = "i2c", "pclk"; 531 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&i2c2_xfer>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 }; 538 539 i2c3: i2c@ff130000 { 540 compatible = "rockchip,rk3399-i2c"; 541 reg = <0x0 0xff130000 0x0 0x1000>; 542 assigned-clocks = <&cru SCLK_I2C3>; 543 assigned-clock-rates = <200000000>; 544 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 545 clock-names = "i2c", "pclk"; 546 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c3_xfer>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 i2c5: i2c@ff140000 { 555 compatible = "rockchip,rk3399-i2c"; 556 reg = <0x0 0xff140000 0x0 0x1000>; 557 assigned-clocks = <&cru SCLK_I2C5>; 558 assigned-clock-rates = <200000000>; 559 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 560 clock-names = "i2c", "pclk"; 561 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&i2c5_xfer>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 status = "disabled"; 567 }; 568 569 i2c6: i2c@ff150000 { 570 compatible = "rockchip,rk3399-i2c"; 571 reg = <0x0 0xff150000 0x0 0x1000>; 572 assigned-clocks = <&cru SCLK_I2C6>; 573 assigned-clock-rates = <200000000>; 574 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 575 clock-names = "i2c", "pclk"; 576 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&i2c6_xfer>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 i2c7: i2c@ff160000 { 585 compatible = "rockchip,rk3399-i2c"; 586 reg = <0x0 0xff160000 0x0 0x1000>; 587 assigned-clocks = <&cru SCLK_I2C7>; 588 assigned-clock-rates = <200000000>; 589 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 590 clock-names = "i2c", "pclk"; 591 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&i2c7_xfer>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 status = "disabled"; 597 }; 598 599 uart0: serial@ff180000 { 600 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 601 reg = <0x0 0xff180000 0x0 0x100>; 602 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 603 clock-names = "baudclk", "apb_pclk"; 604 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 605 reg-shift = <2>; 606 reg-io-width = <4>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&uart0_xfer>; 609 status = "disabled"; 610 }; 611 612 uart1: serial@ff190000 { 613 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 614 reg = <0x0 0xff190000 0x0 0x100>; 615 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 616 clock-names = "baudclk", "apb_pclk"; 617 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 618 reg-shift = <2>; 619 reg-io-width = <4>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&uart1_xfer>; 622 status = "disabled"; 623 }; 624 625 uart2: serial@ff1a0000 { 626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 627 reg = <0x0 0xff1a0000 0x0 0x100>; 628 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 629 clock-names = "baudclk", "apb_pclk"; 630 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 631 reg-shift = <2>; 632 reg-io-width = <4>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&uart2c_xfer>; 635 status = "disabled"; 636 }; 637 638 uart3: serial@ff1b0000 { 639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 640 reg = <0x0 0xff1b0000 0x0 0x100>; 641 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 642 clock-names = "baudclk", "apb_pclk"; 643 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 644 reg-shift = <2>; 645 reg-io-width = <4>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&uart3_xfer>; 648 status = "disabled"; 649 }; 650 651 spi0: spi@ff1c0000 { 652 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 653 reg = <0x0 0xff1c0000 0x0 0x1000>; 654 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 655 clock-names = "spiclk", "apb_pclk"; 656 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 spi1: spi@ff1d0000 { 665 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 666 reg = <0x0 0xff1d0000 0x0 0x1000>; 667 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 668 clock-names = "spiclk", "apb_pclk"; 669 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 spi2: spi@ff1e0000 { 678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 679 reg = <0x0 0xff1e0000 0x0 0x1000>; 680 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 681 clock-names = "spiclk", "apb_pclk"; 682 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 status = "disabled"; 688 }; 689 690 spi4: spi@ff1f0000 { 691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 692 reg = <0x0 0xff1f0000 0x0 0x1000>; 693 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 694 clock-names = "spiclk", "apb_pclk"; 695 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 spi5: spi@ff200000 { 704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 705 reg = <0x0 0xff200000 0x0 0x1000>; 706 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 707 clock-names = "spiclk", "apb_pclk"; 708 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 711 power-domains = <&power RK3399_PD_SDIOAUDIO>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 status = "disabled"; 715 }; 716 717 thermal_zones: thermal-zones { 718 cpu_thermal: cpu { 719 polling-delay-passive = <100>; 720 polling-delay = <1000>; 721 722 thermal-sensors = <&tsadc 0>; 723 724 trips { 725 cpu_alert0: cpu_alert0 { 726 temperature = <70000>; 727 hysteresis = <2000>; 728 type = "passive"; 729 }; 730 cpu_alert1: cpu_alert1 { 731 temperature = <75000>; 732 hysteresis = <2000>; 733 type = "passive"; 734 }; 735 cpu_crit: cpu_crit { 736 temperature = <95000>; 737 hysteresis = <2000>; 738 type = "critical"; 739 }; 740 }; 741 742 cooling-maps { 743 map0 { 744 trip = <&cpu_alert0>; 745 cooling-device = 746 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 747 }; 748 map1 { 749 trip = <&cpu_alert1>; 750 cooling-device = 751 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 752 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 753 }; 754 }; 755 }; 756 757 gpu_thermal: gpu { 758 polling-delay-passive = <100>; 759 polling-delay = <1000>; 760 761 thermal-sensors = <&tsadc 1>; 762 763 trips { 764 gpu_alert0: gpu_alert0 { 765 temperature = <75000>; 766 hysteresis = <2000>; 767 type = "passive"; 768 }; 769 gpu_crit: gpu_crit { 770 temperature = <95000>; 771 hysteresis = <2000>; 772 type = "critical"; 773 }; 774 }; 775 776 cooling-maps { 777 map0 { 778 trip = <&gpu_alert0>; 779 cooling-device = 780 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 781 }; 782 }; 783 }; 784 }; 785 786 tsadc: tsadc@ff260000 { 787 compatible = "rockchip,rk3399-tsadc"; 788 reg = <0x0 0xff260000 0x0 0x100>; 789 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 790 assigned-clocks = <&cru SCLK_TSADC>; 791 assigned-clock-rates = <750000>; 792 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 793 clock-names = "tsadc", "apb_pclk"; 794 resets = <&cru SRST_TSADC>; 795 reset-names = "tsadc-apb"; 796 rockchip,grf = <&grf>; 797 rockchip,hw-tshut-temp = <95000>; 798 pinctrl-names = "init", "default", "sleep"; 799 pinctrl-0 = <&otp_gpio>; 800 pinctrl-1 = <&otp_out>; 801 pinctrl-2 = <&otp_gpio>; 802 #thermal-sensor-cells = <1>; 803 status = "disabled"; 804 }; 805 806 qos_emmc: qos@ffa58000 { 807 compatible = "syscon"; 808 reg = <0x0 0xffa58000 0x0 0x20>; 809 }; 810 811 qos_gmac: qos@ffa5c000 { 812 compatible = "syscon"; 813 reg = <0x0 0xffa5c000 0x0 0x20>; 814 }; 815 816 qos_pcie: qos@ffa60080 { 817 compatible = "syscon"; 818 reg = <0x0 0xffa60080 0x0 0x20>; 819 }; 820 821 qos_usb_host0: qos@ffa60100 { 822 compatible = "syscon"; 823 reg = <0x0 0xffa60100 0x0 0x20>; 824 }; 825 826 qos_usb_host1: qos@ffa60180 { 827 compatible = "syscon"; 828 reg = <0x0 0xffa60180 0x0 0x20>; 829 }; 830 831 qos_usb_otg0: qos@ffa70000 { 832 compatible = "syscon"; 833 reg = <0x0 0xffa70000 0x0 0x20>; 834 }; 835 836 qos_usb_otg1: qos@ffa70080 { 837 compatible = "syscon"; 838 reg = <0x0 0xffa70080 0x0 0x20>; 839 }; 840 841 qos_sd: qos@ffa74000 { 842 compatible = "syscon"; 843 reg = <0x0 0xffa74000 0x0 0x20>; 844 }; 845 846 qos_sdioaudio: qos@ffa76000 { 847 compatible = "syscon"; 848 reg = <0x0 0xffa76000 0x0 0x20>; 849 }; 850 851 qos_hdcp: qos@ffa90000 { 852 compatible = "syscon"; 853 reg = <0x0 0xffa90000 0x0 0x20>; 854 }; 855 856 qos_iep: qos@ffa98000 { 857 compatible = "syscon"; 858 reg = <0x0 0xffa98000 0x0 0x20>; 859 }; 860 861 qos_isp0_m0: qos@ffaa0000 { 862 compatible = "syscon"; 863 reg = <0x0 0xffaa0000 0x0 0x20>; 864 }; 865 866 qos_isp0_m1: qos@ffaa0080 { 867 compatible = "syscon"; 868 reg = <0x0 0xffaa0080 0x0 0x20>; 869 }; 870 871 qos_isp1_m0: qos@ffaa8000 { 872 compatible = "syscon"; 873 reg = <0x0 0xffaa8000 0x0 0x20>; 874 }; 875 876 qos_isp1_m1: qos@ffaa8080 { 877 compatible = "syscon"; 878 reg = <0x0 0xffaa8080 0x0 0x20>; 879 }; 880 881 qos_rga_r: qos@ffab0000 { 882 compatible = "syscon"; 883 reg = <0x0 0xffab0000 0x0 0x20>; 884 }; 885 886 qos_rga_w: qos@ffab0080 { 887 compatible = "syscon"; 888 reg = <0x0 0xffab0080 0x0 0x20>; 889 }; 890 891 qos_video_m0: qos@ffab8000 { 892 compatible = "syscon"; 893 reg = <0x0 0xffab8000 0x0 0x20>; 894 }; 895 896 qos_video_m1_r: qos@ffac0000 { 897 compatible = "syscon"; 898 reg = <0x0 0xffac0000 0x0 0x20>; 899 }; 900 901 qos_video_m1_w: qos@ffac0080 { 902 compatible = "syscon"; 903 reg = <0x0 0xffac0080 0x0 0x20>; 904 }; 905 906 qos_vop_big_r: qos@ffac8000 { 907 compatible = "syscon"; 908 reg = <0x0 0xffac8000 0x0 0x20>; 909 }; 910 911 qos_vop_big_w: qos@ffac8080 { 912 compatible = "syscon"; 913 reg = <0x0 0xffac8080 0x0 0x20>; 914 }; 915 916 qos_vop_little: qos@ffad0000 { 917 compatible = "syscon"; 918 reg = <0x0 0xffad0000 0x0 0x20>; 919 }; 920 921 qos_perihp: qos@ffad8080 { 922 compatible = "syscon"; 923 reg = <0x0 0xffad8080 0x0 0x20>; 924 }; 925 926 qos_gpu: qos@ffae0000 { 927 compatible = "syscon"; 928 reg = <0x0 0xffae0000 0x0 0x20>; 929 }; 930 931 pmu: power-management@ff310000 { 932 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 933 reg = <0x0 0xff310000 0x0 0x1000>; 934 935 /* 936 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 937 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 938 * Some of the power domains are grouped together for every 939 * voltage domain. 940 * The detail contents as below. 941 */ 942 power: power-controller { 943 compatible = "rockchip,rk3399-power-controller"; 944 #power-domain-cells = <1>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 948 /* These power domains are grouped by VD_CENTER */ 949 pd_iep@RK3399_PD_IEP { 950 reg = <RK3399_PD_IEP>; 951 clocks = <&cru ACLK_IEP>, 952 <&cru HCLK_IEP>; 953 pm_qos = <&qos_iep>; 954 }; 955 pd_rga@RK3399_PD_RGA { 956 reg = <RK3399_PD_RGA>; 957 clocks = <&cru ACLK_RGA>, 958 <&cru HCLK_RGA>; 959 pm_qos = <&qos_rga_r>, 960 <&qos_rga_w>; 961 }; 962 pd_vcodec@RK3399_PD_VCODEC { 963 reg = <RK3399_PD_VCODEC>; 964 clocks = <&cru ACLK_VCODEC>, 965 <&cru HCLK_VCODEC>; 966 pm_qos = <&qos_video_m0>; 967 }; 968 pd_vdu@RK3399_PD_VDU { 969 reg = <RK3399_PD_VDU>; 970 clocks = <&cru ACLK_VDU>, 971 <&cru HCLK_VDU>; 972 pm_qos = <&qos_video_m1_r>, 973 <&qos_video_m1_w>; 974 }; 975 976 /* These power domains are grouped by VD_GPU */ 977 pd_gpu@RK3399_PD_GPU { 978 reg = <RK3399_PD_GPU>; 979 clocks = <&cru ACLK_GPU>; 980 pm_qos = <&qos_gpu>; 981 }; 982 983 /* These power domains are grouped by VD_LOGIC */ 984 pd_edp@RK3399_PD_EDP { 985 reg = <RK3399_PD_EDP>; 986 clocks = <&cru PCLK_EDP_CTRL>; 987 }; 988 pd_emmc@RK3399_PD_EMMC { 989 reg = <RK3399_PD_EMMC>; 990 clocks = <&cru ACLK_EMMC>; 991 pm_qos = <&qos_emmc>; 992 }; 993 pd_gmac@RK3399_PD_GMAC { 994 reg = <RK3399_PD_GMAC>; 995 clocks = <&cru ACLK_GMAC>, 996 <&cru PCLK_GMAC>; 997 pm_qos = <&qos_gmac>; 998 }; 999 pd_sd@RK3399_PD_SD { 1000 reg = <RK3399_PD_SD>; 1001 clocks = <&cru HCLK_SDMMC>, 1002 <&cru SCLK_SDMMC>; 1003 pm_qos = <&qos_sd>; 1004 }; 1005 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1006 reg = <RK3399_PD_SDIOAUDIO>; 1007 clocks = <&cru HCLK_SDIO>; 1008 pm_qos = <&qos_sdioaudio>; 1009 }; 1010 pd_usb3@RK3399_PD_USB3 { 1011 reg = <RK3399_PD_USB3>; 1012 clocks = <&cru ACLK_USB3>; 1013 pm_qos = <&qos_usb_otg0>, 1014 <&qos_usb_otg1>; 1015 }; 1016 pd_vio@RK3399_PD_VIO { 1017 reg = <RK3399_PD_VIO>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 1021 pd_hdcp@RK3399_PD_HDCP { 1022 reg = <RK3399_PD_HDCP>; 1023 clocks = <&cru ACLK_HDCP>, 1024 <&cru HCLK_HDCP>, 1025 <&cru PCLK_HDCP>; 1026 pm_qos = <&qos_hdcp>; 1027 }; 1028 pd_isp0@RK3399_PD_ISP0 { 1029 reg = <RK3399_PD_ISP0>; 1030 clocks = <&cru ACLK_ISP0>, 1031 <&cru HCLK_ISP0>; 1032 pm_qos = <&qos_isp0_m0>, 1033 <&qos_isp0_m1>; 1034 }; 1035 pd_isp1@RK3399_PD_ISP1 { 1036 reg = <RK3399_PD_ISP1>; 1037 clocks = <&cru ACLK_ISP1>, 1038 <&cru HCLK_ISP1>; 1039 pm_qos = <&qos_isp1_m0>, 1040 <&qos_isp1_m1>; 1041 }; 1042 pd_tcpc0@RK3399_PD_TCPC0 { 1043 reg = <RK3399_PD_TCPD0>; 1044 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1045 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1046 }; 1047 pd_tcpc1@RK3399_PD_TCPC1 { 1048 reg = <RK3399_PD_TCPD1>; 1049 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1050 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1051 }; 1052 pd_vo@RK3399_PD_VO { 1053 reg = <RK3399_PD_VO>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 1057 pd_vopb@RK3399_PD_VOPB { 1058 reg = <RK3399_PD_VOPB>; 1059 clocks = <&cru ACLK_VOP0>, 1060 <&cru HCLK_VOP0>; 1061 pm_qos = <&qos_vop_big_r>, 1062 <&qos_vop_big_w>; 1063 }; 1064 pd_vopl@RK3399_PD_VOPL { 1065 reg = <RK3399_PD_VOPL>; 1066 clocks = <&cru ACLK_VOP1>, 1067 <&cru HCLK_VOP1>; 1068 pm_qos = <&qos_vop_little>; 1069 }; 1070 }; 1071 }; 1072 }; 1073 }; 1074 1075 pmugrf: syscon@ff320000 { 1076 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1077 reg = <0x0 0xff320000 0x0 0x1000>; 1078 #address-cells = <1>; 1079 #size-cells = <1>; 1080 1081 pmu_io_domains: io-domains { 1082 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1083 status = "disabled"; 1084 }; 1085 }; 1086 1087 spi3: spi@ff350000 { 1088 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1089 reg = <0x0 0xff350000 0x0 0x1000>; 1090 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1091 clock-names = "spiclk", "apb_pclk"; 1092 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 uart4: serial@ff370000 { 1101 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1102 reg = <0x0 0xff370000 0x0 0x100>; 1103 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1104 clock-names = "baudclk", "apb_pclk"; 1105 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1106 reg-shift = <2>; 1107 reg-io-width = <4>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&uart4_xfer>; 1110 status = "disabled"; 1111 }; 1112 1113 i2c0: i2c@ff3c0000 { 1114 compatible = "rockchip,rk3399-i2c"; 1115 reg = <0x0 0xff3c0000 0x0 0x1000>; 1116 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1117 assigned-clock-rates = <200000000>; 1118 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1119 clock-names = "i2c", "pclk"; 1120 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&i2c0_xfer>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 i2c4: i2c@ff3d0000 { 1129 compatible = "rockchip,rk3399-i2c"; 1130 reg = <0x0 0xff3d0000 0x0 0x1000>; 1131 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1132 assigned-clock-rates = <200000000>; 1133 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1134 clock-names = "i2c", "pclk"; 1135 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&i2c4_xfer>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 i2c8: i2c@ff3e0000 { 1144 compatible = "rockchip,rk3399-i2c"; 1145 reg = <0x0 0xff3e0000 0x0 0x1000>; 1146 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1147 assigned-clock-rates = <200000000>; 1148 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1149 clock-names = "i2c", "pclk"; 1150 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&i2c8_xfer>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 pwm0: pwm@ff420000 { 1159 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1160 reg = <0x0 0xff420000 0x0 0x10>; 1161 #pwm-cells = <3>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&pwm0_pin>; 1164 clocks = <&pmucru PCLK_RKPWM_PMU>; 1165 clock-names = "pwm"; 1166 status = "disabled"; 1167 }; 1168 1169 pwm1: pwm@ff420010 { 1170 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1171 reg = <0x0 0xff420010 0x0 0x10>; 1172 #pwm-cells = <3>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&pwm1_pin>; 1175 clocks = <&pmucru PCLK_RKPWM_PMU>; 1176 clock-names = "pwm"; 1177 status = "disabled"; 1178 }; 1179 1180 pwm2: pwm@ff420020 { 1181 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1182 reg = <0x0 0xff420020 0x0 0x10>; 1183 #pwm-cells = <3>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&pwm2_pin>; 1186 clocks = <&pmucru PCLK_RKPWM_PMU>; 1187 clock-names = "pwm"; 1188 status = "disabled"; 1189 }; 1190 1191 pwm3: pwm@ff420030 { 1192 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1193 reg = <0x0 0xff420030 0x0 0x10>; 1194 #pwm-cells = <3>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&pwm3a_pin>; 1197 clocks = <&pmucru PCLK_RKPWM_PMU>; 1198 clock-names = "pwm"; 1199 status = "disabled"; 1200 }; 1201 1202 vpu_mmu: iommu@ff650800 { 1203 compatible = "rockchip,iommu"; 1204 reg = <0x0 0xff650800 0x0 0x40>; 1205 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1206 interrupt-names = "vpu_mmu"; 1207 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1208 clock-names = "aclk", "iface"; 1209 #iommu-cells = <0>; 1210 status = "disabled"; 1211 }; 1212 1213 vdec_mmu: iommu@ff660480 { 1214 compatible = "rockchip,iommu"; 1215 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1217 interrupt-names = "vdec_mmu"; 1218 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1219 clock-names = "aclk", "iface"; 1220 #iommu-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 iep_mmu: iommu@ff670800 { 1225 compatible = "rockchip,iommu"; 1226 reg = <0x0 0xff670800 0x0 0x40>; 1227 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1228 interrupt-names = "iep_mmu"; 1229 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1230 clock-names = "aclk", "iface"; 1231 #iommu-cells = <0>; 1232 status = "disabled"; 1233 }; 1234 1235 rga: rga@ff680000 { 1236 compatible = "rockchip,rk3399-rga"; 1237 reg = <0x0 0xff680000 0x0 0x10000>; 1238 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1239 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1240 clock-names = "aclk", "hclk", "sclk"; 1241 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1242 reset-names = "core", "axi", "ahb"; 1243 power-domains = <&power RK3399_PD_RGA>; 1244 }; 1245 1246 efuse0: efuse@ff690000 { 1247 compatible = "rockchip,rk3399-efuse"; 1248 reg = <0x0 0xff690000 0x0 0x80>; 1249 #address-cells = <1>; 1250 #size-cells = <1>; 1251 clocks = <&cru PCLK_EFUSE1024NS>; 1252 clock-names = "pclk_efuse"; 1253 1254 /* Data cells */ 1255 cpu_id: cpu-id@7 { 1256 reg = <0x07 0x10>; 1257 }; 1258 cpub_leakage: cpu-leakage@17 { 1259 reg = <0x17 0x1>; 1260 }; 1261 gpu_leakage: gpu-leakage@18 { 1262 reg = <0x18 0x1>; 1263 }; 1264 center_leakage: center-leakage@19 { 1265 reg = <0x19 0x1>; 1266 }; 1267 cpul_leakage: cpu-leakage@1a { 1268 reg = <0x1a 0x1>; 1269 }; 1270 logic_leakage: logic-leakage@1b { 1271 reg = <0x1b 0x1>; 1272 }; 1273 wafer_info: wafer-info@1c { 1274 reg = <0x1c 0x1>; 1275 }; 1276 }; 1277 1278 pmucru: pmu-clock-controller@ff750000 { 1279 compatible = "rockchip,rk3399-pmucru"; 1280 reg = <0x0 0xff750000 0x0 0x1000>; 1281 rockchip,grf = <&pmugrf>; 1282 #clock-cells = <1>; 1283 #reset-cells = <1>; 1284 assigned-clocks = <&pmucru PLL_PPLL>; 1285 assigned-clock-rates = <676000000>; 1286 }; 1287 1288 cru: clock-controller@ff760000 { 1289 compatible = "rockchip,rk3399-cru"; 1290 reg = <0x0 0xff760000 0x0 0x1000>; 1291 rockchip,grf = <&grf>; 1292 #clock-cells = <1>; 1293 #reset-cells = <1>; 1294 assigned-clocks = 1295 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1296 <&cru PLL_NPLL>, 1297 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1298 <&cru PCLK_PERIHP>, 1299 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1300 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1301 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1302 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1303 <&cru ACLK_GIC_PRE>, 1304 <&cru PCLK_DDR>; 1305 assigned-clock-rates = 1306 <594000000>, <800000000>, 1307 <1000000000>, 1308 <150000000>, <75000000>, 1309 <37500000>, 1310 <100000000>, <100000000>, 1311 <50000000>, <600000000>, 1312 <100000000>, <50000000>, 1313 <400000000>, <400000000>, 1314 <200000000>, 1315 <200000000>; 1316 }; 1317 1318 grf: syscon@ff770000 { 1319 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1320 reg = <0x0 0xff770000 0x0 0x10000>; 1321 #address-cells = <1>; 1322 #size-cells = <1>; 1323 1324 io_domains: io-domains { 1325 compatible = "rockchip,rk3399-io-voltage-domain"; 1326 status = "disabled"; 1327 }; 1328 1329 u2phy0: usb2-phy@e450 { 1330 compatible = "rockchip,rk3399-usb2phy"; 1331 reg = <0xe450 0x10>; 1332 clocks = <&cru SCLK_USB2PHY0_REF>; 1333 clock-names = "phyclk"; 1334 #clock-cells = <0>; 1335 clock-output-names = "clk_usbphy0_480m"; 1336 status = "disabled"; 1337 1338 u2phy0_host: host-port { 1339 #phy-cells = <0>; 1340 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1341 interrupt-names = "linestate"; 1342 status = "disabled"; 1343 }; 1344 1345 u2phy0_otg: otg-port { 1346 #phy-cells = <0>; 1347 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1348 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1349 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1350 interrupt-names = "otg-bvalid", "otg-id", 1351 "linestate"; 1352 status = "disabled"; 1353 }; 1354 }; 1355 1356 u2phy1: usb2-phy@e460 { 1357 compatible = "rockchip,rk3399-usb2phy"; 1358 reg = <0xe460 0x10>; 1359 clocks = <&cru SCLK_USB2PHY1_REF>; 1360 clock-names = "phyclk"; 1361 #clock-cells = <0>; 1362 clock-output-names = "clk_usbphy1_480m"; 1363 status = "disabled"; 1364 1365 u2phy1_host: host-port { 1366 #phy-cells = <0>; 1367 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1368 interrupt-names = "linestate"; 1369 status = "disabled"; 1370 }; 1371 1372 u2phy1_otg: otg-port { 1373 #phy-cells = <0>; 1374 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1375 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1376 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1377 interrupt-names = "otg-bvalid", "otg-id", 1378 "linestate"; 1379 status = "disabled"; 1380 }; 1381 }; 1382 1383 emmc_phy: phy@f780 { 1384 compatible = "rockchip,rk3399-emmc-phy"; 1385 reg = <0xf780 0x24>; 1386 clocks = <&sdhci>; 1387 clock-names = "emmcclk"; 1388 #phy-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 pcie_phy: pcie-phy { 1393 compatible = "rockchip,rk3399-pcie-phy"; 1394 clocks = <&cru SCLK_PCIEPHY_REF>; 1395 clock-names = "refclk"; 1396 #phy-cells = <1>; 1397 resets = <&cru SRST_PCIEPHY>; 1398 reset-names = "phy"; 1399 status = "disabled"; 1400 }; 1401 }; 1402 1403 tcphy0: phy@ff7c0000 { 1404 compatible = "rockchip,rk3399-typec-phy"; 1405 reg = <0x0 0xff7c0000 0x0 0x40000>; 1406 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1407 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1408 clock-names = "tcpdcore", "tcpdphy-ref"; 1409 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1410 assigned-clock-rates = <50000000>; 1411 power-domains = <&power RK3399_PD_TCPD0>; 1412 resets = <&cru SRST_UPHY0>, 1413 <&cru SRST_UPHY0_PIPE_L00>, 1414 <&cru SRST_P_UPHY0_TCPHY>; 1415 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1416 rockchip,grf = <&grf>; 1417 status = "disabled"; 1418 1419 tcphy0_dp: dp-port { 1420 #phy-cells = <0>; 1421 }; 1422 1423 tcphy0_usb3: usb3-port { 1424 #phy-cells = <0>; 1425 }; 1426 }; 1427 1428 tcphy1: phy@ff800000 { 1429 compatible = "rockchip,rk3399-typec-phy"; 1430 reg = <0x0 0xff800000 0x0 0x40000>; 1431 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1432 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1433 clock-names = "tcpdcore", "tcpdphy-ref"; 1434 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1435 assigned-clock-rates = <50000000>; 1436 power-domains = <&power RK3399_PD_TCPD1>; 1437 resets = <&cru SRST_UPHY1>, 1438 <&cru SRST_UPHY1_PIPE_L00>, 1439 <&cru SRST_P_UPHY1_TCPHY>; 1440 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1441 rockchip,grf = <&grf>; 1442 status = "disabled"; 1443 1444 tcphy1_dp: dp-port { 1445 #phy-cells = <0>; 1446 }; 1447 1448 tcphy1_usb3: usb3-port { 1449 #phy-cells = <0>; 1450 }; 1451 }; 1452 1453 watchdog@ff848000 { 1454 compatible = "snps,dw-wdt"; 1455 reg = <0x0 0xff848000 0x0 0x100>; 1456 clocks = <&cru PCLK_WDT>; 1457 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1458 }; 1459 1460 rktimer: rktimer@ff850000 { 1461 compatible = "rockchip,rk3399-timer"; 1462 reg = <0x0 0xff850000 0x0 0x1000>; 1463 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1464 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1465 clock-names = "pclk", "timer"; 1466 }; 1467 1468 spdif: spdif@ff870000 { 1469 compatible = "rockchip,rk3399-spdif"; 1470 reg = <0x0 0xff870000 0x0 0x1000>; 1471 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1472 dmas = <&dmac_bus 7>; 1473 dma-names = "tx"; 1474 clock-names = "mclk", "hclk"; 1475 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1476 pinctrl-names = "default"; 1477 pinctrl-0 = <&spdif_bus>; 1478 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1479 #sound-dai-cells = <0>; 1480 status = "disabled"; 1481 }; 1482 1483 i2s0: i2s@ff880000 { 1484 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1485 reg = <0x0 0xff880000 0x0 0x1000>; 1486 rockchip,grf = <&grf>; 1487 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1488 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1489 dma-names = "tx", "rx"; 1490 clock-names = "i2s_clk", "i2s_hclk"; 1491 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&i2s0_8ch_bus>; 1494 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1495 #sound-dai-cells = <0>; 1496 status = "disabled"; 1497 }; 1498 1499 i2s1: i2s@ff890000 { 1500 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1501 reg = <0x0 0xff890000 0x0 0x1000>; 1502 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1503 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1504 dma-names = "tx", "rx"; 1505 clock-names = "i2s_clk", "i2s_hclk"; 1506 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&i2s1_2ch_bus>; 1509 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1510 #sound-dai-cells = <0>; 1511 status = "disabled"; 1512 }; 1513 1514 i2s2: i2s@ff8a0000 { 1515 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1516 reg = <0x0 0xff8a0000 0x0 0x1000>; 1517 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1518 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1519 dma-names = "tx", "rx"; 1520 clock-names = "i2s_clk", "i2s_hclk"; 1521 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1522 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1523 #sound-dai-cells = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 vopl: vop@ff8f0000 { 1528 compatible = "rockchip,rk3399-vop-lit"; 1529 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1530 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1531 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1532 assigned-clock-rates = <400000000>, <100000000>; 1533 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1534 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1535 iommus = <&vopl_mmu>; 1536 power-domains = <&power RK3399_PD_VOPL>; 1537 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1538 reset-names = "axi", "ahb", "dclk"; 1539 status = "disabled"; 1540 1541 vopl_out: port { 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 1545 vopl_out_mipi: endpoint@0 { 1546 reg = <0>; 1547 remote-endpoint = <&mipi_in_vopl>; 1548 }; 1549 1550 vopl_out_edp: endpoint@1 { 1551 reg = <1>; 1552 remote-endpoint = <&edp_in_vopl>; 1553 }; 1554 1555 vopl_out_hdmi: endpoint@2 { 1556 reg = <2>; 1557 remote-endpoint = <&hdmi_in_vopl>; 1558 }; 1559 1560 vopl_out_mipi1: endpoint@3 { 1561 reg = <3>; 1562 remote-endpoint = <&mipi1_in_vopl>; 1563 }; 1564 1565 vopl_out_dp: endpoint@4 { 1566 reg = <4>; 1567 remote-endpoint = <&dp_in_vopl>; 1568 }; 1569 }; 1570 }; 1571 1572 vopl_mmu: iommu@ff8f3f00 { 1573 compatible = "rockchip,iommu"; 1574 reg = <0x0 0xff8f3f00 0x0 0x100>; 1575 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1576 interrupt-names = "vopl_mmu"; 1577 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1578 clock-names = "aclk", "iface"; 1579 power-domains = <&power RK3399_PD_VOPL>; 1580 #iommu-cells = <0>; 1581 status = "disabled"; 1582 }; 1583 1584 vopb: vop@ff900000 { 1585 compatible = "rockchip,rk3399-vop-big"; 1586 reg = <0x0 0xff900000 0x0 0x3efc>; 1587 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1588 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1589 assigned-clock-rates = <400000000>, <100000000>; 1590 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1591 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1592 iommus = <&vopb_mmu>; 1593 power-domains = <&power RK3399_PD_VOPB>; 1594 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1595 reset-names = "axi", "ahb", "dclk"; 1596 status = "disabled"; 1597 1598 vopb_out: port { 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 1602 vopb_out_edp: endpoint@0 { 1603 reg = <0>; 1604 remote-endpoint = <&edp_in_vopb>; 1605 }; 1606 1607 vopb_out_mipi: endpoint@1 { 1608 reg = <1>; 1609 remote-endpoint = <&mipi_in_vopb>; 1610 }; 1611 1612 vopb_out_hdmi: endpoint@2 { 1613 reg = <2>; 1614 remote-endpoint = <&hdmi_in_vopb>; 1615 }; 1616 1617 vopb_out_mipi1: endpoint@3 { 1618 reg = <3>; 1619 remote-endpoint = <&mipi1_in_vopb>; 1620 }; 1621 1622 vopb_out_dp: endpoint@4 { 1623 reg = <4>; 1624 remote-endpoint = <&dp_in_vopb>; 1625 }; 1626 }; 1627 }; 1628 1629 vopb_mmu: iommu@ff903f00 { 1630 compatible = "rockchip,iommu"; 1631 reg = <0x0 0xff903f00 0x0 0x100>; 1632 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1633 interrupt-names = "vopb_mmu"; 1634 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1635 clock-names = "aclk", "iface"; 1636 power-domains = <&power RK3399_PD_VOPB>; 1637 #iommu-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 isp0_mmu: iommu@ff914000 { 1642 compatible = "rockchip,iommu"; 1643 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1644 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1645 interrupt-names = "isp0_mmu"; 1646 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1647 clock-names = "aclk", "iface"; 1648 #iommu-cells = <0>; 1649 power-domains = <&power RK3399_PD_ISP0>; 1650 rockchip,disable-mmu-reset; 1651 }; 1652 1653 isp1_mmu: iommu@ff924000 { 1654 compatible = "rockchip,iommu"; 1655 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1656 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1657 interrupt-names = "isp1_mmu"; 1658 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1659 clock-names = "aclk", "iface"; 1660 #iommu-cells = <0>; 1661 power-domains = <&power RK3399_PD_ISP1>; 1662 rockchip,disable-mmu-reset; 1663 }; 1664 1665 hdmi_sound: hdmi-sound { 1666 compatible = "simple-audio-card"; 1667 simple-audio-card,format = "i2s"; 1668 simple-audio-card,mclk-fs = <256>; 1669 simple-audio-card,name = "hdmi-sound"; 1670 status = "disabled"; 1671 1672 simple-audio-card,cpu { 1673 sound-dai = <&i2s2>; 1674 }; 1675 simple-audio-card,codec { 1676 sound-dai = <&hdmi>; 1677 }; 1678 }; 1679 1680 hdmi: hdmi@ff940000 { 1681 compatible = "rockchip,rk3399-dw-hdmi"; 1682 reg = <0x0 0xff940000 0x0 0x20000>; 1683 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1684 clocks = <&cru PCLK_HDMI_CTRL>, 1685 <&cru SCLK_HDMI_SFR>, 1686 <&cru PLL_VPLL>, 1687 <&cru PCLK_VIO_GRF>, 1688 <&cru SCLK_HDMI_CEC>; 1689 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1690 power-domains = <&power RK3399_PD_HDCP>; 1691 reg-io-width = <4>; 1692 rockchip,grf = <&grf>; 1693 #sound-dai-cells = <0>; 1694 status = "disabled"; 1695 1696 ports { 1697 hdmi_in: port { 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 1701 hdmi_in_vopb: endpoint@0 { 1702 reg = <0>; 1703 remote-endpoint = <&vopb_out_hdmi>; 1704 }; 1705 hdmi_in_vopl: endpoint@1 { 1706 reg = <1>; 1707 remote-endpoint = <&vopl_out_hdmi>; 1708 }; 1709 }; 1710 }; 1711 }; 1712 1713 mipi_dsi: mipi@ff960000 { 1714 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1715 reg = <0x0 0xff960000 0x0 0x8000>; 1716 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1717 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1718 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1719 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1720 power-domains = <&power RK3399_PD_VIO>; 1721 resets = <&cru SRST_P_MIPI_DSI0>; 1722 reset-names = "apb"; 1723 rockchip,grf = <&grf>; 1724 status = "disabled"; 1725 1726 ports { 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 1730 mipi_in: port@0 { 1731 reg = <0>; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 mipi_in_vopb: endpoint@0 { 1736 reg = <0>; 1737 remote-endpoint = <&vopb_out_mipi>; 1738 }; 1739 mipi_in_vopl: endpoint@1 { 1740 reg = <1>; 1741 remote-endpoint = <&vopl_out_mipi>; 1742 }; 1743 }; 1744 }; 1745 }; 1746 1747 mipi_dsi1: mipi@ff968000 { 1748 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1749 reg = <0x0 0xff968000 0x0 0x8000>; 1750 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1751 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1752 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1753 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1754 power-domains = <&power RK3399_PD_VIO>; 1755 resets = <&cru SRST_P_MIPI_DSI1>; 1756 reset-names = "apb"; 1757 rockchip,grf = <&grf>; 1758 status = "disabled"; 1759 1760 ports { 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 1764 mipi1_in: port@0 { 1765 reg = <0>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 1769 mipi1_in_vopb: endpoint@0 { 1770 reg = <0>; 1771 remote-endpoint = <&vopb_out_mipi1>; 1772 }; 1773 1774 mipi1_in_vopl: endpoint@1 { 1775 reg = <1>; 1776 remote-endpoint = <&vopl_out_mipi1>; 1777 }; 1778 }; 1779 }; 1780 }; 1781 1782 edp: edp@ff970000 { 1783 compatible = "rockchip,rk3399-edp"; 1784 reg = <0x0 0xff970000 0x0 0x8000>; 1785 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1786 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1787 clock-names = "dp", "pclk", "grf"; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&edp_hpd>; 1790 power-domains = <&power RK3399_PD_EDP>; 1791 resets = <&cru SRST_P_EDP_CTRL>; 1792 reset-names = "dp"; 1793 rockchip,grf = <&grf>; 1794 status = "disabled"; 1795 1796 ports { 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 edp_in: port@0 { 1800 reg = <0>; 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 1804 edp_in_vopb: endpoint@0 { 1805 reg = <0>; 1806 remote-endpoint = <&vopb_out_edp>; 1807 }; 1808 1809 edp_in_vopl: endpoint@1 { 1810 reg = <1>; 1811 remote-endpoint = <&vopl_out_edp>; 1812 }; 1813 }; 1814 }; 1815 }; 1816 1817 gpu: gpu@ff9a0000 { 1818 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1819 reg = <0x0 0xff9a0000 0x0 0x10000>; 1820 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1821 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1822 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1823 interrupt-names = "job", "mmu", "gpu"; 1824 clocks = <&cru ACLK_GPU>; 1825 power-domains = <&power RK3399_PD_GPU>; 1826 status = "disabled"; 1827 }; 1828 1829 pinctrl: pinctrl { 1830 compatible = "rockchip,rk3399-pinctrl"; 1831 rockchip,grf = <&grf>; 1832 rockchip,pmu = <&pmugrf>; 1833 #address-cells = <2>; 1834 #size-cells = <2>; 1835 ranges; 1836 1837 gpio0: gpio0@ff720000 { 1838 compatible = "rockchip,gpio-bank"; 1839 reg = <0x0 0xff720000 0x0 0x100>; 1840 clocks = <&pmucru PCLK_GPIO0_PMU>; 1841 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1842 1843 gpio-controller; 1844 #gpio-cells = <0x2>; 1845 1846 interrupt-controller; 1847 #interrupt-cells = <0x2>; 1848 }; 1849 1850 gpio1: gpio1@ff730000 { 1851 compatible = "rockchip,gpio-bank"; 1852 reg = <0x0 0xff730000 0x0 0x100>; 1853 clocks = <&pmucru PCLK_GPIO1_PMU>; 1854 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1855 1856 gpio-controller; 1857 #gpio-cells = <0x2>; 1858 1859 interrupt-controller; 1860 #interrupt-cells = <0x2>; 1861 }; 1862 1863 gpio2: gpio2@ff780000 { 1864 compatible = "rockchip,gpio-bank"; 1865 reg = <0x0 0xff780000 0x0 0x100>; 1866 clocks = <&cru PCLK_GPIO2>; 1867 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1868 1869 gpio-controller; 1870 #gpio-cells = <0x2>; 1871 1872 interrupt-controller; 1873 #interrupt-cells = <0x2>; 1874 }; 1875 1876 gpio3: gpio3@ff788000 { 1877 compatible = "rockchip,gpio-bank"; 1878 reg = <0x0 0xff788000 0x0 0x100>; 1879 clocks = <&cru PCLK_GPIO3>; 1880 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1881 1882 gpio-controller; 1883 #gpio-cells = <0x2>; 1884 1885 interrupt-controller; 1886 #interrupt-cells = <0x2>; 1887 }; 1888 1889 gpio4: gpio4@ff790000 { 1890 compatible = "rockchip,gpio-bank"; 1891 reg = <0x0 0xff790000 0x0 0x100>; 1892 clocks = <&cru PCLK_GPIO4>; 1893 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1894 1895 gpio-controller; 1896 #gpio-cells = <0x2>; 1897 1898 interrupt-controller; 1899 #interrupt-cells = <0x2>; 1900 }; 1901 1902 pcfg_pull_up: pcfg-pull-up { 1903 bias-pull-up; 1904 }; 1905 1906 pcfg_pull_down: pcfg-pull-down { 1907 bias-pull-down; 1908 }; 1909 1910 pcfg_pull_none: pcfg-pull-none { 1911 bias-disable; 1912 }; 1913 1914 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1915 bias-disable; 1916 drive-strength = <12>; 1917 }; 1918 1919 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1920 bias-disable; 1921 drive-strength = <13>; 1922 }; 1923 1924 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1925 bias-disable; 1926 drive-strength = <18>; 1927 }; 1928 1929 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 1930 bias-disable; 1931 drive-strength = <20>; 1932 }; 1933 1934 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1935 bias-pull-up; 1936 drive-strength = <2>; 1937 }; 1938 1939 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1940 bias-pull-up; 1941 drive-strength = <8>; 1942 }; 1943 1944 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 1945 bias-pull-up; 1946 drive-strength = <18>; 1947 }; 1948 1949 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 1950 bias-pull-up; 1951 drive-strength = <20>; 1952 }; 1953 1954 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1955 bias-pull-down; 1956 drive-strength = <4>; 1957 }; 1958 1959 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 1960 bias-pull-down; 1961 drive-strength = <8>; 1962 }; 1963 1964 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1965 bias-pull-down; 1966 drive-strength = <12>; 1967 }; 1968 1969 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 1970 bias-pull-down; 1971 drive-strength = <18>; 1972 }; 1973 1974 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 1975 bias-pull-down; 1976 drive-strength = <20>; 1977 }; 1978 1979 pcfg_output_high: pcfg-output-high { 1980 output-high; 1981 }; 1982 1983 pcfg_output_low: pcfg-output-low { 1984 output-low; 1985 }; 1986 1987 clock { 1988 clk_32k: clk-32k { 1989 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 1990 }; 1991 }; 1992 1993 edp { 1994 edp_hpd: edp-hpd { 1995 rockchip,pins = 1996 <4 23 RK_FUNC_2 &pcfg_pull_none>; 1997 }; 1998 }; 1999 2000 gmac { 2001 rgmii_pins: rgmii-pins { 2002 rockchip,pins = 2003 /* mac_txclk */ 2004 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 2005 /* mac_rxclk */ 2006 <3 14 RK_FUNC_1 &pcfg_pull_none>, 2007 /* mac_mdio */ 2008 <3 13 RK_FUNC_1 &pcfg_pull_none>, 2009 /* mac_txen */ 2010 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 2011 /* mac_clk */ 2012 <3 11 RK_FUNC_1 &pcfg_pull_none>, 2013 /* mac_rxdv */ 2014 <3 9 RK_FUNC_1 &pcfg_pull_none>, 2015 /* mac_mdc */ 2016 <3 8 RK_FUNC_1 &pcfg_pull_none>, 2017 /* mac_rxd1 */ 2018 <3 7 RK_FUNC_1 &pcfg_pull_none>, 2019 /* mac_rxd0 */ 2020 <3 6 RK_FUNC_1 &pcfg_pull_none>, 2021 /* mac_txd1 */ 2022 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2023 /* mac_txd0 */ 2024 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 2025 /* mac_rxd3 */ 2026 <3 3 RK_FUNC_1 &pcfg_pull_none>, 2027 /* mac_rxd2 */ 2028 <3 2 RK_FUNC_1 &pcfg_pull_none>, 2029 /* mac_txd3 */ 2030 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 2031 /* mac_txd2 */ 2032 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 2033 }; 2034 2035 rmii_pins: rmii-pins { 2036 rockchip,pins = 2037 /* mac_mdio */ 2038 <3 13 RK_FUNC_1 &pcfg_pull_none>, 2039 /* mac_txen */ 2040 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 2041 /* mac_clk */ 2042 <3 11 RK_FUNC_1 &pcfg_pull_none>, 2043 /* mac_rxer */ 2044 <3 10 RK_FUNC_1 &pcfg_pull_none>, 2045 /* mac_rxdv */ 2046 <3 9 RK_FUNC_1 &pcfg_pull_none>, 2047 /* mac_mdc */ 2048 <3 8 RK_FUNC_1 &pcfg_pull_none>, 2049 /* mac_rxd1 */ 2050 <3 7 RK_FUNC_1 &pcfg_pull_none>, 2051 /* mac_rxd0 */ 2052 <3 6 RK_FUNC_1 &pcfg_pull_none>, 2053 /* mac_txd1 */ 2054 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2055 /* mac_txd0 */ 2056 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 2057 }; 2058 }; 2059 2060 i2c0 { 2061 i2c0_xfer: i2c0-xfer { 2062 rockchip,pins = 2063 <1 15 RK_FUNC_2 &pcfg_pull_none>, 2064 <1 16 RK_FUNC_2 &pcfg_pull_none>; 2065 }; 2066 }; 2067 2068 i2c1 { 2069 i2c1_xfer: i2c1-xfer { 2070 rockchip,pins = 2071 <4 2 RK_FUNC_1 &pcfg_pull_none>, 2072 <4 1 RK_FUNC_1 &pcfg_pull_none>; 2073 }; 2074 }; 2075 2076 i2c2 { 2077 i2c2_xfer: i2c2-xfer { 2078 rockchip,pins = 2079 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2080 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 2081 }; 2082 }; 2083 2084 i2c3 { 2085 i2c3_xfer: i2c3-xfer { 2086 rockchip,pins = 2087 <4 17 RK_FUNC_1 &pcfg_pull_none>, 2088 <4 16 RK_FUNC_1 &pcfg_pull_none>; 2089 }; 2090 }; 2091 2092 i2c4 { 2093 i2c4_xfer: i2c4-xfer { 2094 rockchip,pins = 2095 <1 12 RK_FUNC_1 &pcfg_pull_none>, 2096 <1 11 RK_FUNC_1 &pcfg_pull_none>; 2097 }; 2098 }; 2099 2100 i2c5 { 2101 i2c5_xfer: i2c5-xfer { 2102 rockchip,pins = 2103 <3 11 RK_FUNC_2 &pcfg_pull_none>, 2104 <3 10 RK_FUNC_2 &pcfg_pull_none>; 2105 }; 2106 }; 2107 2108 i2c6 { 2109 i2c6_xfer: i2c6-xfer { 2110 rockchip,pins = 2111 <2 10 RK_FUNC_2 &pcfg_pull_none>, 2112 <2 9 RK_FUNC_2 &pcfg_pull_none>; 2113 }; 2114 }; 2115 2116 i2c7 { 2117 i2c7_xfer: i2c7-xfer { 2118 rockchip,pins = 2119 <2 8 RK_FUNC_2 &pcfg_pull_none>, 2120 <2 7 RK_FUNC_2 &pcfg_pull_none>; 2121 }; 2122 }; 2123 2124 i2c8 { 2125 i2c8_xfer: i2c8-xfer { 2126 rockchip,pins = 2127 <1 21 RK_FUNC_1 &pcfg_pull_none>, 2128 <1 20 RK_FUNC_1 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 i2s0 { 2133 i2s0_2ch_bus: i2s0-2ch-bus { 2134 rockchip,pins = 2135 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2136 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2137 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2138 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2139 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2140 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2141 }; 2142 2143 i2s0_8ch_bus: i2s0-8ch-bus { 2144 rockchip,pins = 2145 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2146 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2147 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2148 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2149 <3 28 RK_FUNC_1 &pcfg_pull_none>, 2150 <3 29 RK_FUNC_1 &pcfg_pull_none>, 2151 <3 30 RK_FUNC_1 &pcfg_pull_none>, 2152 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2153 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2154 }; 2155 }; 2156 2157 i2s1 { 2158 i2s1_2ch_bus: i2s1-2ch-bus { 2159 rockchip,pins = 2160 <4 3 RK_FUNC_1 &pcfg_pull_none>, 2161 <4 4 RK_FUNC_1 &pcfg_pull_none>, 2162 <4 5 RK_FUNC_1 &pcfg_pull_none>, 2163 <4 6 RK_FUNC_1 &pcfg_pull_none>, 2164 <4 7 RK_FUNC_1 &pcfg_pull_none>; 2165 }; 2166 }; 2167 2168 sdio0 { 2169 sdio0_bus1: sdio0-bus1 { 2170 rockchip,pins = 2171 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 2172 }; 2173 2174 sdio0_bus4: sdio0-bus4 { 2175 rockchip,pins = 2176 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 2177 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 2178 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 2179 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 2180 }; 2181 2182 sdio0_cmd: sdio0-cmd { 2183 rockchip,pins = 2184 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 2185 }; 2186 2187 sdio0_clk: sdio0-clk { 2188 rockchip,pins = 2189 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 2190 }; 2191 2192 sdio0_cd: sdio0-cd { 2193 rockchip,pins = 2194 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 2195 }; 2196 2197 sdio0_pwr: sdio0-pwr { 2198 rockchip,pins = 2199 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 2200 }; 2201 2202 sdio0_bkpwr: sdio0-bkpwr { 2203 rockchip,pins = 2204 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 2205 }; 2206 2207 sdio0_wp: sdio0-wp { 2208 rockchip,pins = 2209 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2210 }; 2211 2212 sdio0_int: sdio0-int { 2213 rockchip,pins = 2214 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2215 }; 2216 }; 2217 2218 sdmmc { 2219 sdmmc_bus1: sdmmc-bus1 { 2220 rockchip,pins = 2221 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2222 }; 2223 2224 sdmmc_bus4: sdmmc-bus4 { 2225 rockchip,pins = 2226 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2227 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2228 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2229 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2230 }; 2231 2232 sdmmc_clk: sdmmc-clk { 2233 rockchip,pins = 2234 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2235 }; 2236 2237 sdmmc_cmd: sdmmc-cmd { 2238 rockchip,pins = 2239 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2240 }; 2241 2242 sdmmc_cd: sdmmc-cd { 2243 rockchip,pins = 2244 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2245 }; 2246 2247 sdmmc_wp: sdmmc-wp { 2248 rockchip,pins = 2249 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2250 }; 2251 }; 2252 2253 sleep { 2254 ap_pwroff: ap-pwroff { 2255 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 2256 }; 2257 2258 ddrio_pwroff: ddrio-pwroff { 2259 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 2260 }; 2261 }; 2262 2263 spdif { 2264 spdif_bus: spdif-bus { 2265 rockchip,pins = 2266 <4 21 RK_FUNC_1 &pcfg_pull_none>; 2267 }; 2268 2269 spdif_bus_1: spdif-bus-1 { 2270 rockchip,pins = 2271 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2272 }; 2273 }; 2274 2275 spi0 { 2276 spi0_clk: spi0-clk { 2277 rockchip,pins = 2278 <3 6 RK_FUNC_2 &pcfg_pull_up>; 2279 }; 2280 spi0_cs0: spi0-cs0 { 2281 rockchip,pins = 2282 <3 7 RK_FUNC_2 &pcfg_pull_up>; 2283 }; 2284 spi0_cs1: spi0-cs1 { 2285 rockchip,pins = 2286 <3 8 RK_FUNC_2 &pcfg_pull_up>; 2287 }; 2288 spi0_tx: spi0-tx { 2289 rockchip,pins = 2290 <3 5 RK_FUNC_2 &pcfg_pull_up>; 2291 }; 2292 spi0_rx: spi0-rx { 2293 rockchip,pins = 2294 <3 4 RK_FUNC_2 &pcfg_pull_up>; 2295 }; 2296 }; 2297 2298 spi1 { 2299 spi1_clk: spi1-clk { 2300 rockchip,pins = 2301 <1 9 RK_FUNC_2 &pcfg_pull_up>; 2302 }; 2303 spi1_cs0: spi1-cs0 { 2304 rockchip,pins = 2305 <1 10 RK_FUNC_2 &pcfg_pull_up>; 2306 }; 2307 spi1_rx: spi1-rx { 2308 rockchip,pins = 2309 <1 7 RK_FUNC_2 &pcfg_pull_up>; 2310 }; 2311 spi1_tx: spi1-tx { 2312 rockchip,pins = 2313 <1 8 RK_FUNC_2 &pcfg_pull_up>; 2314 }; 2315 }; 2316 2317 spi2 { 2318 spi2_clk: spi2-clk { 2319 rockchip,pins = 2320 <2 11 RK_FUNC_1 &pcfg_pull_up>; 2321 }; 2322 spi2_cs0: spi2-cs0 { 2323 rockchip,pins = 2324 <2 12 RK_FUNC_1 &pcfg_pull_up>; 2325 }; 2326 spi2_rx: spi2-rx { 2327 rockchip,pins = 2328 <2 9 RK_FUNC_1 &pcfg_pull_up>; 2329 }; 2330 spi2_tx: spi2-tx { 2331 rockchip,pins = 2332 <2 10 RK_FUNC_1 &pcfg_pull_up>; 2333 }; 2334 }; 2335 2336 spi3 { 2337 spi3_clk: spi3-clk { 2338 rockchip,pins = 2339 <1 17 RK_FUNC_1 &pcfg_pull_up>; 2340 }; 2341 spi3_cs0: spi3-cs0 { 2342 rockchip,pins = 2343 <1 18 RK_FUNC_1 &pcfg_pull_up>; 2344 }; 2345 spi3_rx: spi3-rx { 2346 rockchip,pins = 2347 <1 15 RK_FUNC_1 &pcfg_pull_up>; 2348 }; 2349 spi3_tx: spi3-tx { 2350 rockchip,pins = 2351 <1 16 RK_FUNC_1 &pcfg_pull_up>; 2352 }; 2353 }; 2354 2355 spi4 { 2356 spi4_clk: spi4-clk { 2357 rockchip,pins = 2358 <3 2 RK_FUNC_2 &pcfg_pull_up>; 2359 }; 2360 spi4_cs0: spi4-cs0 { 2361 rockchip,pins = 2362 <3 3 RK_FUNC_2 &pcfg_pull_up>; 2363 }; 2364 spi4_rx: spi4-rx { 2365 rockchip,pins = 2366 <3 0 RK_FUNC_2 &pcfg_pull_up>; 2367 }; 2368 spi4_tx: spi4-tx { 2369 rockchip,pins = 2370 <3 1 RK_FUNC_2 &pcfg_pull_up>; 2371 }; 2372 }; 2373 2374 spi5 { 2375 spi5_clk: spi5-clk { 2376 rockchip,pins = 2377 <2 22 RK_FUNC_2 &pcfg_pull_up>; 2378 }; 2379 spi5_cs0: spi5-cs0 { 2380 rockchip,pins = 2381 <2 23 RK_FUNC_2 &pcfg_pull_up>; 2382 }; 2383 spi5_rx: spi5-rx { 2384 rockchip,pins = 2385 <2 20 RK_FUNC_2 &pcfg_pull_up>; 2386 }; 2387 spi5_tx: spi5-tx { 2388 rockchip,pins = 2389 <2 21 RK_FUNC_2 &pcfg_pull_up>; 2390 }; 2391 }; 2392 2393 testclk { 2394 test_clkout0: test-clkout0 { 2395 rockchip,pins = 2396 <0 0 RK_FUNC_1 &pcfg_pull_none>; 2397 }; 2398 2399 test_clkout1: test-clkout1 { 2400 rockchip,pins = 2401 <2 25 RK_FUNC_2 &pcfg_pull_none>; 2402 }; 2403 2404 test_clkout2: test-clkout2 { 2405 rockchip,pins = 2406 <0 8 RK_FUNC_3 &pcfg_pull_none>; 2407 }; 2408 }; 2409 2410 tsadc { 2411 otp_gpio: otp-gpio { 2412 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 2413 }; 2414 2415 otp_out: otp-out { 2416 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 2417 }; 2418 }; 2419 2420 uart0 { 2421 uart0_xfer: uart0-xfer { 2422 rockchip,pins = 2423 <2 16 RK_FUNC_1 &pcfg_pull_up>, 2424 <2 17 RK_FUNC_1 &pcfg_pull_none>; 2425 }; 2426 2427 uart0_cts: uart0-cts { 2428 rockchip,pins = 2429 <2 18 RK_FUNC_1 &pcfg_pull_none>; 2430 }; 2431 2432 uart0_rts: uart0-rts { 2433 rockchip,pins = 2434 <2 19 RK_FUNC_1 &pcfg_pull_none>; 2435 }; 2436 }; 2437 2438 uart1 { 2439 uart1_xfer: uart1-xfer { 2440 rockchip,pins = 2441 <3 12 RK_FUNC_2 &pcfg_pull_up>, 2442 <3 13 RK_FUNC_2 &pcfg_pull_none>; 2443 }; 2444 }; 2445 2446 uart2a { 2447 uart2a_xfer: uart2a-xfer { 2448 rockchip,pins = 2449 <4 8 RK_FUNC_2 &pcfg_pull_up>, 2450 <4 9 RK_FUNC_2 &pcfg_pull_none>; 2451 }; 2452 }; 2453 2454 uart2b { 2455 uart2b_xfer: uart2b-xfer { 2456 rockchip,pins = 2457 <4 16 RK_FUNC_2 &pcfg_pull_up>, 2458 <4 17 RK_FUNC_2 &pcfg_pull_none>; 2459 }; 2460 }; 2461 2462 uart2c { 2463 uart2c_xfer: uart2c-xfer { 2464 rockchip,pins = 2465 <4 19 RK_FUNC_1 &pcfg_pull_up>, 2466 <4 20 RK_FUNC_1 &pcfg_pull_none>; 2467 }; 2468 }; 2469 2470 uart3 { 2471 uart3_xfer: uart3-xfer { 2472 rockchip,pins = 2473 <3 14 RK_FUNC_2 &pcfg_pull_up>, 2474 <3 15 RK_FUNC_2 &pcfg_pull_none>; 2475 }; 2476 2477 uart3_cts: uart3-cts { 2478 rockchip,pins = 2479 <3 18 RK_FUNC_2 &pcfg_pull_none>; 2480 }; 2481 2482 uart3_rts: uart3-rts { 2483 rockchip,pins = 2484 <3 19 RK_FUNC_2 &pcfg_pull_none>; 2485 }; 2486 }; 2487 2488 uart4 { 2489 uart4_xfer: uart4-xfer { 2490 rockchip,pins = 2491 <1 7 RK_FUNC_1 &pcfg_pull_up>, 2492 <1 8 RK_FUNC_1 &pcfg_pull_none>; 2493 }; 2494 }; 2495 2496 uarthdcp { 2497 uarthdcp_xfer: uarthdcp-xfer { 2498 rockchip,pins = 2499 <4 21 RK_FUNC_2 &pcfg_pull_up>, 2500 <4 22 RK_FUNC_2 &pcfg_pull_none>; 2501 }; 2502 }; 2503 2504 pwm0 { 2505 pwm0_pin: pwm0-pin { 2506 rockchip,pins = 2507 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2508 }; 2509 2510 pwm0_pin_pull_down: pwm0-pin-pull-down { 2511 rockchip,pins = 2512 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>; 2513 }; 2514 2515 vop0_pwm_pin: vop0-pwm-pin { 2516 rockchip,pins = 2517 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2518 }; 2519 2520 vop1_pwm_pin: vop1-pwm-pin { 2521 rockchip,pins = 2522 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2523 }; 2524 }; 2525 2526 pwm1 { 2527 pwm1_pin: pwm1-pin { 2528 rockchip,pins = 2529 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2530 }; 2531 2532 pwm1_pin_pull_down: pwm1-pin-pull-down { 2533 rockchip,pins = 2534 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>; 2535 }; 2536 }; 2537 2538 pwm2 { 2539 pwm2_pin: pwm2-pin { 2540 rockchip,pins = 2541 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2542 }; 2543 2544 pwm2_pin_pull_down: pwm2-pin-pull-down { 2545 rockchip,pins = 2546 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; 2547 }; 2548 }; 2549 2550 pwm3a { 2551 pwm3a_pin: pwm3a-pin { 2552 rockchip,pins = 2553 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2554 }; 2555 }; 2556 2557 pwm3b { 2558 pwm3b_pin: pwm3b-pin { 2559 rockchip,pins = 2560 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2561 }; 2562 }; 2563 2564 hdmi { 2565 hdmi_i2c_xfer: hdmi-i2c-xfer { 2566 rockchip,pins = 2567 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2568 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2569 }; 2570 2571 hdmi_cec: hdmi-cec { 2572 rockchip,pins = 2573 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2574 }; 2575 }; 2576 2577 pcie { 2578 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2579 rockchip,pins = 2580 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2581 }; 2582 2583 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2584 rockchip,pins = 2585 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2586 }; 2587 }; 2588 2589 }; 2590}; 2591