1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas System Solutions Asia Pte. Ltd - Migo-R
4 *
5 * Copyright (C) 2008 Magnus Damm
6 */
7 #include <linux/clkdev.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/interrupt.h>
12 #include <linux/input.h>
13 #include <linux/input/sh_keysc.h>
14 #include <linux/memblock.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/mfd/tmio.h>
18 #include <linux/mtd/rawnand.h>
19 #include <linux/i2c.h>
20 #include <linux/regulator/fixed.h>
21 #include <linux/regulator/machine.h>
22 #include <linux/smc91x.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/gpio.h>
26 #include <linux/gpio/machine.h>
27 #include <linux/videodev2.h>
28 #include <linux/sh_intc.h>
29 #include <video/sh_mobile_lcdc.h>
30 #include <media/drv-intf/renesas-ceu.h>
31 #include <media/i2c/ov772x.h>
32 #include <media/i2c/tw9910.h>
33 #include <asm/clock.h>
34 #include <asm/machvec.h>
35 #include <asm/io.h>
36 #include <asm/suspend.h>
37 #include <mach/migor.h>
38 #include <cpu/sh7722.h>
39
40 /* Address IRQ Size Bus Description
41 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
42 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
43 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
44 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
45 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
46 */
47
48 #define CEU_BUFFER_MEMORY_SIZE (4 << 20)
49 static phys_addr_t ceu_dma_membase;
50
51 static struct smc91x_platdata smc91x_info = {
52 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
53 };
54
55 static struct resource smc91x_eth_resources[] = {
56 [0] = {
57 .name = "SMC91C111" ,
58 .start = 0x10000300,
59 .end = 0x1000030f,
60 .flags = IORESOURCE_MEM,
61 },
62 [1] = {
63 .start = evt2irq(0x600), /* IRQ0 */
64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
65 },
66 };
67
68 static struct platform_device smc91x_eth_device = {
69 .name = "smc91x",
70 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
71 .resource = smc91x_eth_resources,
72 .dev = {
73 .platform_data = &smc91x_info,
74 },
75 };
76
77 static struct sh_keysc_info sh_keysc_info = {
78 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
79 .scan_timing = 3,
80 .delay = 5,
81 .keycodes = {
82 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
83 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
84 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
85 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
86 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
87 },
88 };
89
90 static struct resource sh_keysc_resources[] = {
91 [0] = {
92 .start = 0x044b0000,
93 .end = 0x044b000f,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = evt2irq(0xbe0),
98 .flags = IORESOURCE_IRQ,
99 },
100 };
101
102 static struct platform_device sh_keysc_device = {
103 .name = "sh_keysc",
104 .id = 0, /* "keysc0" clock */
105 .num_resources = ARRAY_SIZE(sh_keysc_resources),
106 .resource = sh_keysc_resources,
107 .dev = {
108 .platform_data = &sh_keysc_info,
109 },
110 };
111
112 static struct mtd_partition migor_nor_flash_partitions[] =
113 {
114 {
115 .name = "uboot",
116 .offset = 0,
117 .size = (1 * 1024 * 1024),
118 .mask_flags = MTD_WRITEABLE, /* Read-only */
119 },
120 {
121 .name = "rootfs",
122 .offset = MTDPART_OFS_APPEND,
123 .size = (15 * 1024 * 1024),
124 },
125 {
126 .name = "other",
127 .offset = MTDPART_OFS_APPEND,
128 .size = MTDPART_SIZ_FULL,
129 },
130 };
131
132 static struct physmap_flash_data migor_nor_flash_data = {
133 .width = 2,
134 .parts = migor_nor_flash_partitions,
135 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
136 };
137
138 static struct resource migor_nor_flash_resources[] = {
139 [0] = {
140 .name = "NOR Flash",
141 .start = 0x00000000,
142 .end = 0x03ffffff,
143 .flags = IORESOURCE_MEM,
144 }
145 };
146
147 static struct platform_device migor_nor_flash_device = {
148 .name = "physmap-flash",
149 .resource = migor_nor_flash_resources,
150 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
151 .dev = {
152 .platform_data = &migor_nor_flash_data,
153 },
154 };
155
156 static struct mtd_partition migor_nand_flash_partitions[] = {
157 {
158 .name = "nanddata1",
159 .offset = 0x0,
160 .size = 512 * 1024 * 1024,
161 },
162 {
163 .name = "nanddata2",
164 .offset = MTDPART_OFS_APPEND,
165 .size = 512 * 1024 * 1024,
166 },
167 };
168
migor_nand_flash_cmd_ctl(struct mtd_info * mtd,int cmd,unsigned int ctrl)169 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
170 unsigned int ctrl)
171 {
172 struct nand_chip *chip = mtd_to_nand(mtd);
173
174 if (cmd == NAND_CMD_NONE)
175 return;
176
177 if (ctrl & NAND_CLE)
178 writeb(cmd, chip->IO_ADDR_W + 0x00400000);
179 else if (ctrl & NAND_ALE)
180 writeb(cmd, chip->IO_ADDR_W + 0x00800000);
181 else
182 writeb(cmd, chip->IO_ADDR_W);
183 }
184
migor_nand_flash_ready(struct mtd_info * mtd)185 static int migor_nand_flash_ready(struct mtd_info *mtd)
186 {
187 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
188 }
189
190 static struct platform_nand_data migor_nand_flash_data = {
191 .chip = {
192 .nr_chips = 1,
193 .partitions = migor_nand_flash_partitions,
194 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
195 .chip_delay = 20,
196 },
197 .ctrl = {
198 .dev_ready = migor_nand_flash_ready,
199 .cmd_ctrl = migor_nand_flash_cmd_ctl,
200 },
201 };
202
203 static struct resource migor_nand_flash_resources[] = {
204 [0] = {
205 .name = "NAND Flash",
206 .start = 0x18000000,
207 .end = 0x18ffffff,
208 .flags = IORESOURCE_MEM,
209 },
210 };
211
212 static struct platform_device migor_nand_flash_device = {
213 .name = "gen_nand",
214 .resource = migor_nand_flash_resources,
215 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
216 .dev = {
217 .platform_data = &migor_nand_flash_data,
218 }
219 };
220
221 static const struct fb_videomode migor_lcd_modes[] = {
222 {
223 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
224 .name = "LB070WV1",
225 .xres = 800,
226 .yres = 480,
227 .left_margin = 64,
228 .right_margin = 16,
229 .hsync_len = 120,
230 .sync = 0,
231 #elif defined(CONFIG_SH_MIGOR_QVGA)
232 .name = "PH240320T",
233 .xres = 320,
234 .yres = 240,
235 .left_margin = 0,
236 .right_margin = 16,
237 .hsync_len = 8,
238 .sync = FB_SYNC_HOR_HIGH_ACT,
239 #endif
240 .upper_margin = 1,
241 .lower_margin = 17,
242 .vsync_len = 2,
243 },
244 };
245
246 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
247 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
248 .clock_source = LCDC_CLK_BUS,
249 .ch[0] = {
250 .chan = LCDC_CHAN_MAINLCD,
251 .fourcc = V4L2_PIX_FMT_RGB565,
252 .interface_type = RGB16,
253 .clock_divider = 2,
254 .lcd_modes = migor_lcd_modes,
255 .num_modes = ARRAY_SIZE(migor_lcd_modes),
256 .panel_cfg = { /* 7.0 inch */
257 .width = 152,
258 .height = 91,
259 },
260 }
261 #elif defined(CONFIG_SH_MIGOR_QVGA)
262 .clock_source = LCDC_CLK_PERIPHERAL,
263 .ch[0] = {
264 .chan = LCDC_CHAN_MAINLCD,
265 .fourcc = V4L2_PIX_FMT_RGB565,
266 .interface_type = SYS16A,
267 .clock_divider = 10,
268 .lcd_modes = migor_lcd_modes,
269 .num_modes = ARRAY_SIZE(migor_lcd_modes),
270 .panel_cfg = {
271 .width = 49, /* 2.4 inch */
272 .height = 37,
273 .setup_sys = migor_lcd_qvga_setup,
274 },
275 .sys_bus_cfg = {
276 .ldmt2r = 0x06000a09,
277 .ldmt3r = 0x180e3418,
278 /* set 1s delay to encourage fsync() */
279 .deferred_io_msec = 1000,
280 },
281 }
282 #endif
283 };
284
285 static struct resource migor_lcdc_resources[] = {
286 [0] = {
287 .name = "LCDC",
288 .start = 0xfe940000, /* P4-only space */
289 .end = 0xfe942fff,
290 .flags = IORESOURCE_MEM,
291 },
292 [1] = {
293 .start = evt2irq(0x580),
294 .flags = IORESOURCE_IRQ,
295 },
296 };
297
298 static struct platform_device migor_lcdc_device = {
299 .name = "sh_mobile_lcdc_fb",
300 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
301 .resource = migor_lcdc_resources,
302 .dev = {
303 .platform_data = &sh_mobile_lcdc_info,
304 },
305 };
306
307 static struct ceu_platform_data ceu_pdata = {
308 .num_subdevs = 2,
309 .subdevs = {
310 { /* [0] = ov772x */
311 .flags = 0,
312 .bus_width = 8,
313 .bus_shift = 0,
314 .i2c_adapter_id = 0,
315 .i2c_address = 0x21,
316 },
317 { /* [1] = tw9910 */
318 .flags = 0,
319 .bus_width = 8,
320 .bus_shift = 0,
321 .i2c_adapter_id = 0,
322 .i2c_address = 0x45,
323 },
324 },
325 };
326
327 static struct resource migor_ceu_resources[] = {
328 [0] = {
329 .name = "CEU",
330 .start = 0xfe910000,
331 .end = 0xfe91009f,
332 .flags = IORESOURCE_MEM,
333 },
334 [1] = {
335 .start = evt2irq(0x880),
336 .flags = IORESOURCE_IRQ,
337 },
338 };
339
340 static struct platform_device migor_ceu_device = {
341 .name = "renesas-ceu",
342 .id = 0, /* ceu.0 */
343 .num_resources = ARRAY_SIZE(migor_ceu_resources),
344 .resource = migor_ceu_resources,
345 .dev = {
346 .platform_data = &ceu_pdata,
347 },
348 };
349
350 /* Powerdown/reset gpios for CEU image sensors */
351 static struct gpiod_lookup_table ov7725_gpios = {
352 .dev_id = "0-0021",
353 .table = {
354 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
355 GPIO_ACTIVE_HIGH),
356 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
357 },
358 };
359
360 static struct gpiod_lookup_table tw9910_gpios = {
361 .dev_id = "0-0045",
362 .table = {
363 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
364 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
365 },
366 };
367
368 /* Fixed 3.3V regulator to be used by SDHI0 */
369 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
370 {
371 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
372 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
373 };
374
375 static struct resource sdhi_cn9_resources[] = {
376 [0] = {
377 .name = "SDHI",
378 .start = 0x04ce0000,
379 .end = 0x04ce00ff,
380 .flags = IORESOURCE_MEM,
381 },
382 [1] = {
383 .start = evt2irq(0xe80),
384 .flags = IORESOURCE_IRQ,
385 },
386 };
387
388 static struct tmio_mmc_data sh7724_sdhi_data = {
389 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
390 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
391 .capabilities = MMC_CAP_SDIO_IRQ,
392 };
393
394 static struct platform_device sdhi_cn9_device = {
395 .name = "sh_mobile_sdhi",
396 .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
397 .resource = sdhi_cn9_resources,
398 .dev = {
399 .platform_data = &sh7724_sdhi_data,
400 },
401 };
402
403 static struct ov772x_camera_info ov7725_info = {
404 .flags = 0,
405 };
406
407 static struct tw9910_video_info tw9910_info = {
408 .buswidth = 8,
409 .mpout = TW9910_MPO_FIELD,
410 };
411
412 static struct i2c_board_info migor_i2c_devices[] = {
413 {
414 I2C_BOARD_INFO("rs5c372b", 0x32),
415 },
416 {
417 I2C_BOARD_INFO("migor_ts", 0x51),
418 .irq = evt2irq(0x6c0), /* IRQ6 */
419 },
420 {
421 I2C_BOARD_INFO("wm8978", 0x1a),
422 },
423 {
424 I2C_BOARD_INFO("ov772x", 0x21),
425 .platform_data = &ov7725_info,
426 },
427 {
428 I2C_BOARD_INFO("tw9910", 0x45),
429 .platform_data = &tw9910_info,
430 },
431 };
432
433 static struct platform_device *migor_devices[] __initdata = {
434 &smc91x_eth_device,
435 &sh_keysc_device,
436 &migor_lcdc_device,
437 &migor_nor_flash_device,
438 &migor_nand_flash_device,
439 &sdhi_cn9_device,
440 };
441
442 extern char migor_sdram_enter_start;
443 extern char migor_sdram_enter_end;
444 extern char migor_sdram_leave_start;
445 extern char migor_sdram_leave_end;
446
migor_devices_setup(void)447 static int __init migor_devices_setup(void)
448 {
449 struct clk *video_clk;
450
451 /* register board specific self-refresh code */
452 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
453 &migor_sdram_enter_start,
454 &migor_sdram_enter_end,
455 &migor_sdram_leave_start,
456 &migor_sdram_leave_end);
457
458 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
459 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
460
461 /* Let D11 LED show STATUS0 */
462 gpio_request(GPIO_FN_STATUS0, NULL);
463
464 /* Lit D12 LED show PDSTATUS */
465 gpio_request(GPIO_FN_PDSTATUS, NULL);
466
467 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
468 gpio_request(GPIO_FN_IRQ0, NULL);
469 __raw_writel(0x00003400, BSC_CS4BCR);
470 __raw_writel(0x00110080, BSC_CS4WCR);
471
472 /* KEYSC */
473 gpio_request(GPIO_FN_KEYOUT0, NULL);
474 gpio_request(GPIO_FN_KEYOUT1, NULL);
475 gpio_request(GPIO_FN_KEYOUT2, NULL);
476 gpio_request(GPIO_FN_KEYOUT3, NULL);
477 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
478 gpio_request(GPIO_FN_KEYIN1, NULL);
479 gpio_request(GPIO_FN_KEYIN2, NULL);
480 gpio_request(GPIO_FN_KEYIN3, NULL);
481 gpio_request(GPIO_FN_KEYIN4, NULL);
482 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
483
484 /* NAND Flash */
485 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
486 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
487 gpio_request(GPIO_PTA1, NULL);
488 gpio_direction_input(GPIO_PTA1);
489
490 /* SDHI */
491 gpio_request(GPIO_FN_SDHICD, NULL);
492 gpio_request(GPIO_FN_SDHIWP, NULL);
493 gpio_request(GPIO_FN_SDHID3, NULL);
494 gpio_request(GPIO_FN_SDHID2, NULL);
495 gpio_request(GPIO_FN_SDHID1, NULL);
496 gpio_request(GPIO_FN_SDHID0, NULL);
497 gpio_request(GPIO_FN_SDHICMD, NULL);
498 gpio_request(GPIO_FN_SDHICLK, NULL);
499
500 /* Touch Panel */
501 gpio_request(GPIO_FN_IRQ6, NULL);
502
503 /* LCD Panel */
504 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
505 gpio_request(GPIO_FN_LCDD17, NULL);
506 gpio_request(GPIO_FN_LCDD16, NULL);
507 gpio_request(GPIO_FN_LCDD15, NULL);
508 gpio_request(GPIO_FN_LCDD14, NULL);
509 gpio_request(GPIO_FN_LCDD13, NULL);
510 gpio_request(GPIO_FN_LCDD12, NULL);
511 gpio_request(GPIO_FN_LCDD11, NULL);
512 gpio_request(GPIO_FN_LCDD10, NULL);
513 gpio_request(GPIO_FN_LCDD8, NULL);
514 gpio_request(GPIO_FN_LCDD7, NULL);
515 gpio_request(GPIO_FN_LCDD6, NULL);
516 gpio_request(GPIO_FN_LCDD5, NULL);
517 gpio_request(GPIO_FN_LCDD4, NULL);
518 gpio_request(GPIO_FN_LCDD3, NULL);
519 gpio_request(GPIO_FN_LCDD2, NULL);
520 gpio_request(GPIO_FN_LCDD1, NULL);
521 gpio_request(GPIO_FN_LCDRS, NULL);
522 gpio_request(GPIO_FN_LCDCS, NULL);
523 gpio_request(GPIO_FN_LCDRD, NULL);
524 gpio_request(GPIO_FN_LCDWR, NULL);
525 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
526 gpio_direction_output(GPIO_PTH2, 1);
527 #endif
528 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
529 gpio_request(GPIO_FN_LCDD15, NULL);
530 gpio_request(GPIO_FN_LCDD14, NULL);
531 gpio_request(GPIO_FN_LCDD13, NULL);
532 gpio_request(GPIO_FN_LCDD12, NULL);
533 gpio_request(GPIO_FN_LCDD11, NULL);
534 gpio_request(GPIO_FN_LCDD10, NULL);
535 gpio_request(GPIO_FN_LCDD9, NULL);
536 gpio_request(GPIO_FN_LCDD8, NULL);
537 gpio_request(GPIO_FN_LCDD7, NULL);
538 gpio_request(GPIO_FN_LCDD6, NULL);
539 gpio_request(GPIO_FN_LCDD5, NULL);
540 gpio_request(GPIO_FN_LCDD4, NULL);
541 gpio_request(GPIO_FN_LCDD3, NULL);
542 gpio_request(GPIO_FN_LCDD2, NULL);
543 gpio_request(GPIO_FN_LCDD1, NULL);
544 gpio_request(GPIO_FN_LCDD0, NULL);
545 gpio_request(GPIO_FN_LCDLCLK, NULL);
546 gpio_request(GPIO_FN_LCDDCK, NULL);
547 gpio_request(GPIO_FN_LCDVEPWC, NULL);
548 gpio_request(GPIO_FN_LCDVCPWC, NULL);
549 gpio_request(GPIO_FN_LCDVSYN, NULL);
550 gpio_request(GPIO_FN_LCDHSYN, NULL);
551 gpio_request(GPIO_FN_LCDDISP, NULL);
552 gpio_request(GPIO_FN_LCDDON, NULL);
553 #endif
554
555 /* CEU */
556 gpio_request(GPIO_FN_VIO_CLK2, NULL);
557 gpio_request(GPIO_FN_VIO_VD2, NULL);
558 gpio_request(GPIO_FN_VIO_HD2, NULL);
559 gpio_request(GPIO_FN_VIO_FLD, NULL);
560 gpio_request(GPIO_FN_VIO_CKO, NULL);
561 gpio_request(GPIO_FN_VIO_D15, NULL);
562 gpio_request(GPIO_FN_VIO_D14, NULL);
563 gpio_request(GPIO_FN_VIO_D13, NULL);
564 gpio_request(GPIO_FN_VIO_D12, NULL);
565 gpio_request(GPIO_FN_VIO_D11, NULL);
566 gpio_request(GPIO_FN_VIO_D10, NULL);
567 gpio_request(GPIO_FN_VIO_D9, NULL);
568 gpio_request(GPIO_FN_VIO_D8, NULL);
569
570 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
571
572 /* SIU: Port B */
573 gpio_request(GPIO_FN_SIUBOLR, NULL);
574 gpio_request(GPIO_FN_SIUBOBT, NULL);
575 gpio_request(GPIO_FN_SIUBISLD, NULL);
576 gpio_request(GPIO_FN_SIUBOSLD, NULL);
577 gpio_request(GPIO_FN_SIUMCKB, NULL);
578
579 /*
580 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
581 * output. Need only SIUB, set to output for master mode (table 34.2)
582 */
583 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
584
585 /*
586 * Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
587 * issues on Panel Board V2.1.
588 */
589 video_clk = clk_get(NULL, "video_clk");
590 if (!IS_ERR(video_clk)) {
591 clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
592 clk_put(video_clk);
593 }
594
595 /* Add a clock alias for ov7725 xclk source. */
596 clk_add_alias(NULL, "0-0021", "video_clk", NULL);
597
598 /* Register GPIOs for video sources. */
599 gpiod_add_lookup_table(&ov7725_gpios);
600 gpiod_add_lookup_table(&tw9910_gpios);
601
602 i2c_register_board_info(0, migor_i2c_devices,
603 ARRAY_SIZE(migor_i2c_devices));
604
605 /* Initialize CEU platform device separately to map memory first */
606 device_initialize(&migor_ceu_device.dev);
607 arch_setup_pdev_archdata(&migor_ceu_device);
608 dma_declare_coherent_memory(&migor_ceu_device.dev,
609 ceu_dma_membase, ceu_dma_membase,
610 ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
611 DMA_MEMORY_EXCLUSIVE);
612
613 platform_device_add(&migor_ceu_device);
614
615 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
616 }
617 arch_initcall(migor_devices_setup);
618
619 /* Return the board specific boot mode pin configuration */
migor_mode_pins(void)620 static int migor_mode_pins(void)
621 {
622 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
623 * MD3=0: 16-bit Area0 Bus Width
624 * MD5=1: Little Endian
625 * TSTMD=1, MD8=0: Test Mode Disabled
626 */
627 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
628 }
629
630 /* Reserve a portion of memory for CEU buffers */
migor_mv_mem_reserve(void)631 static void __init migor_mv_mem_reserve(void)
632 {
633 phys_addr_t phys;
634 phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
635
636 phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
637 memblock_free(phys, size);
638 memblock_remove(phys, size);
639
640 ceu_dma_membase = phys;
641 }
642
643 /*
644 * The Machine Vector
645 */
646 static struct sh_machine_vector mv_migor __initmv = {
647 .mv_name = "Migo-R",
648 .mv_mode_pins = migor_mode_pins,
649 .mv_mem_reserve = migor_mv_mem_reserve,
650 };
651