1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
51 #include "ahci.h"
52
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
55
56 enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
62 };
63
64 enum board_ids {
65 /* board IDs by feature in alphabetical order */
66 board_ahci,
67 board_ahci_ign_iferr,
68 board_ahci_mobile,
69 board_ahci_nomsi,
70 board_ahci_noncq,
71 board_ahci_nosntf,
72 board_ahci_yes_fbs,
73
74 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_avn,
76 board_ahci_mcp65,
77 board_ahci_mcp77,
78 board_ahci_mcp89,
79 board_ahci_mv,
80 board_ahci_sb600,
81 board_ahci_sb700, /* for SB700 and SB800 */
82 board_ahci_vt8251,
83
84 /*
85 * board IDs for Intel chipsets that support more than 6 ports
86 * *and* end up needing the PCS quirk.
87 */
88 board_ahci_pcs7,
89
90 /* aliases */
91 board_ahci_mcp_linux = board_ahci_mcp65,
92 board_ahci_mcp67 = board_ahci_mcp65,
93 board_ahci_mcp73 = board_ahci_mcp65,
94 board_ahci_mcp79 = board_ahci_mcp77,
95 };
96
97 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
98 static void ahci_remove_one(struct pci_dev *dev);
99 static void ahci_shutdown_one(struct pci_dev *dev);
100 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
101 unsigned long deadline);
102 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
103 unsigned long deadline);
104 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
105 static bool is_mcp89_apple(struct pci_dev *pdev);
106 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
107 unsigned long deadline);
108 #ifdef CONFIG_PM
109 static int ahci_pci_device_runtime_suspend(struct device *dev);
110 static int ahci_pci_device_runtime_resume(struct device *dev);
111 #ifdef CONFIG_PM_SLEEP
112 static int ahci_pci_device_suspend(struct device *dev);
113 static int ahci_pci_device_resume(struct device *dev);
114 #endif
115 #endif /* CONFIG_PM */
116
117 static struct scsi_host_template ahci_sht = {
118 AHCI_SHT("ahci"),
119 };
120
121 static struct ata_port_operations ahci_vt8251_ops = {
122 .inherits = &ahci_ops,
123 .hardreset = ahci_vt8251_hardreset,
124 };
125
126 static struct ata_port_operations ahci_p5wdh_ops = {
127 .inherits = &ahci_ops,
128 .hardreset = ahci_p5wdh_hardreset,
129 };
130
131 static struct ata_port_operations ahci_avn_ops = {
132 .inherits = &ahci_ops,
133 .hardreset = ahci_avn_hardreset,
134 };
135
136 static const struct ata_port_info ahci_port_info[] = {
137 /* by features */
138 [board_ahci] = {
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_ign_iferr] = {
145 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_mobile] = {
152 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_nomsi] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_noncq] = {
166 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 [board_ahci_nosntf] = {
173 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
174 .flags = AHCI_FLAG_COMMON,
175 .pio_mask = ATA_PIO4,
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &ahci_ops,
178 },
179 [board_ahci_yes_fbs] = {
180 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
185 },
186 /* by chipsets */
187 [board_ahci_avn] = {
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_avn_ops,
192 },
193 [board_ahci_mcp65] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
195 AHCI_HFLAG_YES_NCQ),
196 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp77] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mcp89] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_ops,
214 },
215 [board_ahci_mv] = {
216 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
217 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
218 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_ops,
222 },
223 [board_ahci_sb600] = {
224 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
225 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
226 AHCI_HFLAG_32BIT_ONLY),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_sb700] = { /* for SB700 and SB800 */
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_pmp_retry_srst_ops,
238 },
239 [board_ahci_vt8251] = {
240 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
241 .flags = AHCI_FLAG_COMMON,
242 .pio_mask = ATA_PIO4,
243 .udma_mask = ATA_UDMA6,
244 .port_ops = &ahci_vt8251_ops,
245 },
246 [board_ahci_pcs7] = {
247 .flags = AHCI_FLAG_COMMON,
248 .pio_mask = ATA_PIO4,
249 .udma_mask = ATA_UDMA6,
250 .port_ops = &ahci_ops,
251 },
252 };
253
254 static const struct pci_device_id ahci_pci_tbl[] = {
255 /* Intel */
256 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
257 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
258 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
259 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
260 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
261 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
262 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
263 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
264 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
265 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
266 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
267 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
268 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
269 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
270 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
271 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
272 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
273 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
278 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
279 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
281 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
283 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
284 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
285 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
286 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
287 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
288 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
289 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
291 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
292 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
293 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
294 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
295 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
317 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
318 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
319 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
320 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
321 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
322 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
323 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
324 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
325 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
326 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
327 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
328 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
329 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
330 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
331 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
332 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
333 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
334 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
335 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
336 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
337 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
338 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
339 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
340 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
341 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
342 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
343 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
344 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
345 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
346 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
347 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
351 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
352 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
354 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
368 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
370 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
374 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
376 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
377 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
378 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
379 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
381 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
382 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
383 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
384 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
385 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
386 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
387 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
389 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
390 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
391 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
392 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
393 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
394 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
395 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
396 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
398 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
399 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
401 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
402 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
404 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
406 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
408 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
411 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
412 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
413 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
415 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
416 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
417 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
418
419 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
420 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
421 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
422 /* JMicron 362B and 362C have an AHCI function with IDE class code */
423 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
424 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
425 /* May need to update quirk_jmicron_async_suspend() for additions */
426
427 /* ATI */
428 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
429 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
430 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
435
436 /* AMD */
437 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
438 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
439 /* AMD is using RAID class only for ahci controllers */
440 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
441 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
442
443 /* VIA */
444 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
445 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
446
447 /* NVIDIA */
448 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
469 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
521 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
522 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
532
533 /* SiS */
534 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
535 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
536 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
537
538 /* ST Microelectronics */
539 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
540
541 /* Marvell */
542 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
543 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
544 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
545 .class = PCI_CLASS_STORAGE_SATA_AHCI,
546 .class_mask = 0xffffff,
547 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
548 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
549 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
550 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
551 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
552 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
554 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
556 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
558 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
562 .driver_data = board_ahci_yes_fbs },
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
564 .driver_data = board_ahci_yes_fbs },
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
566 .driver_data = board_ahci_yes_fbs },
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
572 .driver_data = board_ahci_yes_fbs },
573
574 /* Promise */
575 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
576 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
577
578 /* Asmedia */
579 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
580 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
581 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
582 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
583 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
584 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
585
586 /*
587 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
588 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
589 */
590 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
591 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
592
593 /* Enmotus */
594 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
595
596 /* Generic, PCI class code for AHCI */
597 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
598 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
599
600 { } /* terminate list */
601 };
602
603 static const struct dev_pm_ops ahci_pci_pm_ops = {
604 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
605 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
606 ahci_pci_device_runtime_resume, NULL)
607 };
608
609 static struct pci_driver ahci_pci_driver = {
610 .name = DRV_NAME,
611 .id_table = ahci_pci_tbl,
612 .probe = ahci_init_one,
613 .remove = ahci_remove_one,
614 .shutdown = ahci_shutdown_one,
615 .driver = {
616 .pm = &ahci_pci_pm_ops,
617 },
618 };
619
620 #if IS_ENABLED(CONFIG_PATA_MARVELL)
621 static int marvell_enable;
622 #else
623 static int marvell_enable = 1;
624 #endif
625 module_param(marvell_enable, int, 0644);
626 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
627
628 static int mobile_lpm_policy = -1;
629 module_param(mobile_lpm_policy, int, 0644);
630 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
631
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)632 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
633 struct ahci_host_priv *hpriv)
634 {
635 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
636 dev_info(&pdev->dev, "JMB361 has only one port\n");
637 hpriv->force_port_map = 1;
638 }
639
640 /*
641 * Temporary Marvell 6145 hack: PATA port presence
642 * is asserted through the standard AHCI port
643 * presence register, as bit 4 (counting from 0)
644 */
645 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
646 if (pdev->device == 0x6121)
647 hpriv->mask_port_map = 0x3;
648 else
649 hpriv->mask_port_map = 0xf;
650 dev_info(&pdev->dev,
651 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
652 }
653
654 ahci_save_initial_config(&pdev->dev, hpriv);
655 }
656
ahci_pci_init_controller(struct ata_host * host)657 static void ahci_pci_init_controller(struct ata_host *host)
658 {
659 struct ahci_host_priv *hpriv = host->private_data;
660 struct pci_dev *pdev = to_pci_dev(host->dev);
661 void __iomem *port_mmio;
662 u32 tmp;
663 int mv;
664
665 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
666 if (pdev->device == 0x6121)
667 mv = 2;
668 else
669 mv = 4;
670 port_mmio = __ahci_port_base(host, mv);
671
672 writel(0, port_mmio + PORT_IRQ_MASK);
673
674 /* clear port IRQ */
675 tmp = readl(port_mmio + PORT_IRQ_STAT);
676 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
677 if (tmp)
678 writel(tmp, port_mmio + PORT_IRQ_STAT);
679 }
680
681 ahci_init_controller(host);
682 }
683
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)684 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
685 unsigned long deadline)
686 {
687 struct ata_port *ap = link->ap;
688 struct ahci_host_priv *hpriv = ap->host->private_data;
689 bool online;
690 int rc;
691
692 DPRINTK("ENTER\n");
693
694 hpriv->stop_engine(ap);
695
696 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
697 deadline, &online, NULL);
698
699 hpriv->start_engine(ap);
700
701 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
702
703 /* vt8251 doesn't clear BSY on signature FIS reception,
704 * request follow-up softreset.
705 */
706 return online ? -EAGAIN : rc;
707 }
708
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)709 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
710 unsigned long deadline)
711 {
712 struct ata_port *ap = link->ap;
713 struct ahci_port_priv *pp = ap->private_data;
714 struct ahci_host_priv *hpriv = ap->host->private_data;
715 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
716 struct ata_taskfile tf;
717 bool online;
718 int rc;
719
720 hpriv->stop_engine(ap);
721
722 /* clear D2H reception area to properly wait for D2H FIS */
723 ata_tf_init(link->device, &tf);
724 tf.command = ATA_BUSY;
725 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
726
727 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
728 deadline, &online, NULL);
729
730 hpriv->start_engine(ap);
731
732 /* The pseudo configuration device on SIMG4726 attached to
733 * ASUS P5W-DH Deluxe doesn't send signature FIS after
734 * hardreset if no device is attached to the first downstream
735 * port && the pseudo device locks up on SRST w/ PMP==0. To
736 * work around this, wait for !BSY only briefly. If BSY isn't
737 * cleared, perform CLO and proceed to IDENTIFY (achieved by
738 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
739 *
740 * Wait for two seconds. Devices attached to downstream port
741 * which can't process the following IDENTIFY after this will
742 * have to be reset again. For most cases, this should
743 * suffice while making probing snappish enough.
744 */
745 if (online) {
746 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
747 ahci_check_ready);
748 if (rc)
749 ahci_kick_engine(ap);
750 }
751 return rc;
752 }
753
754 /*
755 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
756 *
757 * It has been observed with some SSDs that the timing of events in the
758 * link synchronization phase can leave the port in a state that can not
759 * be recovered by a SATA-hard-reset alone. The failing signature is
760 * SStatus.DET stuck at 1 ("Device presence detected but Phy
761 * communication not established"). It was found that unloading and
762 * reloading the driver when this problem occurs allows the drive
763 * connection to be recovered (DET advanced to 0x3). The critical
764 * component of reloading the driver is that the port state machines are
765 * reset by bouncing "port enable" in the AHCI PCS configuration
766 * register. So, reproduce that effect by bouncing a port whenever we
767 * see DET==1 after a reset.
768 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)769 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
770 unsigned long deadline)
771 {
772 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
773 struct ata_port *ap = link->ap;
774 struct ahci_port_priv *pp = ap->private_data;
775 struct ahci_host_priv *hpriv = ap->host->private_data;
776 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
777 unsigned long tmo = deadline - jiffies;
778 struct ata_taskfile tf;
779 bool online;
780 int rc, i;
781
782 DPRINTK("ENTER\n");
783
784 hpriv->stop_engine(ap);
785
786 for (i = 0; i < 2; i++) {
787 u16 val;
788 u32 sstatus;
789 int port = ap->port_no;
790 struct ata_host *host = ap->host;
791 struct pci_dev *pdev = to_pci_dev(host->dev);
792
793 /* clear D2H reception area to properly wait for D2H FIS */
794 ata_tf_init(link->device, &tf);
795 tf.command = ATA_BUSY;
796 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
797
798 rc = sata_link_hardreset(link, timing, deadline, &online,
799 ahci_check_ready);
800
801 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
802 (sstatus & 0xf) != 1)
803 break;
804
805 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
806 port);
807
808 pci_read_config_word(pdev, 0x92, &val);
809 val &= ~(1 << port);
810 pci_write_config_word(pdev, 0x92, val);
811 ata_msleep(ap, 1000);
812 val |= 1 << port;
813 pci_write_config_word(pdev, 0x92, val);
814 deadline += tmo;
815 }
816
817 hpriv->start_engine(ap);
818
819 if (online)
820 *class = ahci_dev_classify(ap);
821
822 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
823 return rc;
824 }
825
826
827 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)828 static void ahci_pci_disable_interrupts(struct ata_host *host)
829 {
830 struct ahci_host_priv *hpriv = host->private_data;
831 void __iomem *mmio = hpriv->mmio;
832 u32 ctl;
833
834 /* AHCI spec rev1.1 section 8.3.3:
835 * Software must disable interrupts prior to requesting a
836 * transition of the HBA to D3 state.
837 */
838 ctl = readl(mmio + HOST_CTL);
839 ctl &= ~HOST_IRQ_EN;
840 writel(ctl, mmio + HOST_CTL);
841 readl(mmio + HOST_CTL); /* flush */
842 }
843
ahci_pci_device_runtime_suspend(struct device * dev)844 static int ahci_pci_device_runtime_suspend(struct device *dev)
845 {
846 struct pci_dev *pdev = to_pci_dev(dev);
847 struct ata_host *host = pci_get_drvdata(pdev);
848
849 ahci_pci_disable_interrupts(host);
850 return 0;
851 }
852
ahci_pci_device_runtime_resume(struct device * dev)853 static int ahci_pci_device_runtime_resume(struct device *dev)
854 {
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct ata_host *host = pci_get_drvdata(pdev);
857 int rc;
858
859 rc = ahci_reset_controller(host);
860 if (rc)
861 return rc;
862 ahci_pci_init_controller(host);
863 return 0;
864 }
865
866 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)867 static int ahci_pci_device_suspend(struct device *dev)
868 {
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct ata_host *host = pci_get_drvdata(pdev);
871 struct ahci_host_priv *hpriv = host->private_data;
872
873 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
874 dev_err(&pdev->dev,
875 "BIOS update required for suspend/resume\n");
876 return -EIO;
877 }
878
879 ahci_pci_disable_interrupts(host);
880 return ata_host_suspend(host, PMSG_SUSPEND);
881 }
882
ahci_pci_device_resume(struct device * dev)883 static int ahci_pci_device_resume(struct device *dev)
884 {
885 struct pci_dev *pdev = to_pci_dev(dev);
886 struct ata_host *host = pci_get_drvdata(pdev);
887 int rc;
888
889 /* Apple BIOS helpfully mangles the registers on resume */
890 if (is_mcp89_apple(pdev))
891 ahci_mcp89_apple_enable(pdev);
892
893 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
894 rc = ahci_reset_controller(host);
895 if (rc)
896 return rc;
897
898 ahci_pci_init_controller(host);
899 }
900
901 ata_host_resume(host);
902
903 return 0;
904 }
905 #endif
906
907 #endif /* CONFIG_PM */
908
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)909 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
910 {
911 int rc;
912
913 /*
914 * If the device fixup already set the dma_mask to some non-standard
915 * value, don't extend it here. This happens on STA2X11, for example.
916 */
917 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
918 return 0;
919
920 if (using_dac &&
921 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
922 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
923 if (rc) {
924 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
925 if (rc) {
926 dev_err(&pdev->dev,
927 "64-bit DMA enable failed\n");
928 return rc;
929 }
930 }
931 } else {
932 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
933 if (rc) {
934 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
935 return rc;
936 }
937 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
938 if (rc) {
939 dev_err(&pdev->dev,
940 "32-bit consistent DMA enable failed\n");
941 return rc;
942 }
943 }
944 return 0;
945 }
946
ahci_pci_print_info(struct ata_host * host)947 static void ahci_pci_print_info(struct ata_host *host)
948 {
949 struct pci_dev *pdev = to_pci_dev(host->dev);
950 u16 cc;
951 const char *scc_s;
952
953 pci_read_config_word(pdev, 0x0a, &cc);
954 if (cc == PCI_CLASS_STORAGE_IDE)
955 scc_s = "IDE";
956 else if (cc == PCI_CLASS_STORAGE_SATA)
957 scc_s = "SATA";
958 else if (cc == PCI_CLASS_STORAGE_RAID)
959 scc_s = "RAID";
960 else
961 scc_s = "unknown";
962
963 ahci_print_info(host, scc_s);
964 }
965
966 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
967 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
968 * support PMP and the 4726 either directly exports the device
969 * attached to the first downstream port or acts as a hardware storage
970 * controller and emulate a single ATA device (can be RAID 0/1 or some
971 * other configuration).
972 *
973 * When there's no device attached to the first downstream port of the
974 * 4726, "Config Disk" appears, which is a pseudo ATA device to
975 * configure the 4726. However, ATA emulation of the device is very
976 * lame. It doesn't send signature D2H Reg FIS after the initial
977 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
978 *
979 * The following function works around the problem by always using
980 * hardreset on the port and not depending on receiving signature FIS
981 * afterward. If signature FIS isn't received soon, ATA class is
982 * assumed without follow-up softreset.
983 */
ahci_p5wdh_workaround(struct ata_host * host)984 static void ahci_p5wdh_workaround(struct ata_host *host)
985 {
986 static const struct dmi_system_id sysids[] = {
987 {
988 .ident = "P5W DH Deluxe",
989 .matches = {
990 DMI_MATCH(DMI_SYS_VENDOR,
991 "ASUSTEK COMPUTER INC"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
993 },
994 },
995 { }
996 };
997 struct pci_dev *pdev = to_pci_dev(host->dev);
998
999 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1000 dmi_check_system(sysids)) {
1001 struct ata_port *ap = host->ports[1];
1002
1003 dev_info(&pdev->dev,
1004 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1005
1006 ap->ops = &ahci_p5wdh_ops;
1007 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1008 }
1009 }
1010
1011 /*
1012 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1013 * booting in BIOS compatibility mode. We restore the registers but not ID.
1014 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1015 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1016 {
1017 u32 val;
1018
1019 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1020
1021 pci_read_config_dword(pdev, 0xf8, &val);
1022 val |= 1 << 0x1b;
1023 /* the following changes the device ID, but appears not to affect function */
1024 /* val = (val & ~0xf0000000) | 0x80000000; */
1025 pci_write_config_dword(pdev, 0xf8, val);
1026
1027 pci_read_config_dword(pdev, 0x54c, &val);
1028 val |= 1 << 0xc;
1029 pci_write_config_dword(pdev, 0x54c, val);
1030
1031 pci_read_config_dword(pdev, 0x4a4, &val);
1032 val &= 0xff;
1033 val |= 0x01060100;
1034 pci_write_config_dword(pdev, 0x4a4, val);
1035
1036 pci_read_config_dword(pdev, 0x54c, &val);
1037 val &= ~(1 << 0xc);
1038 pci_write_config_dword(pdev, 0x54c, val);
1039
1040 pci_read_config_dword(pdev, 0xf8, &val);
1041 val &= ~(1 << 0x1b);
1042 pci_write_config_dword(pdev, 0xf8, val);
1043 }
1044
is_mcp89_apple(struct pci_dev * pdev)1045 static bool is_mcp89_apple(struct pci_dev *pdev)
1046 {
1047 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1048 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1049 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1050 pdev->subsystem_device == 0xcb89;
1051 }
1052
1053 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1054 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1055 {
1056 static const struct dmi_system_id sysids[] = {
1057 /*
1058 * The oldest version known to be broken is 0901 and
1059 * working is 1501 which was released on 2007-10-26.
1060 * Enable 64bit DMA on 1501 and anything newer.
1061 *
1062 * Please read bko#9412 for more info.
1063 */
1064 {
1065 .ident = "ASUS M2A-VM",
1066 .matches = {
1067 DMI_MATCH(DMI_BOARD_VENDOR,
1068 "ASUSTeK Computer INC."),
1069 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1070 },
1071 .driver_data = "20071026", /* yyyymmdd */
1072 },
1073 /*
1074 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1075 * support 64bit DMA.
1076 *
1077 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1078 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1079 * This spelling mistake was fixed in BIOS version 1.5, so
1080 * 1.5 and later have the Manufacturer as
1081 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1082 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1083 *
1084 * BIOS versions earlier than 1.9 had a Board Product Name
1085 * DMI field of "MS-7376". This was changed to be
1086 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1087 * match on DMI_BOARD_NAME of "MS-7376".
1088 */
1089 {
1090 .ident = "MSI K9A2 Platinum",
1091 .matches = {
1092 DMI_MATCH(DMI_BOARD_VENDOR,
1093 "MICRO-STAR INTER"),
1094 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1095 },
1096 },
1097 /*
1098 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1099 * 64bit DMA.
1100 *
1101 * This board also had the typo mentioned above in the
1102 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1103 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1104 */
1105 {
1106 .ident = "MSI K9AGM2",
1107 .matches = {
1108 DMI_MATCH(DMI_BOARD_VENDOR,
1109 "MICRO-STAR INTER"),
1110 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1111 },
1112 },
1113 /*
1114 * All BIOS versions for the Asus M3A support 64bit DMA.
1115 * (all release versions from 0301 to 1206 were tested)
1116 */
1117 {
1118 .ident = "ASUS M3A",
1119 .matches = {
1120 DMI_MATCH(DMI_BOARD_VENDOR,
1121 "ASUSTeK Computer INC."),
1122 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1123 },
1124 },
1125 { }
1126 };
1127 const struct dmi_system_id *match;
1128 int year, month, date;
1129 char buf[9];
1130
1131 match = dmi_first_match(sysids);
1132 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1133 !match)
1134 return false;
1135
1136 if (!match->driver_data)
1137 goto enable_64bit;
1138
1139 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1140 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1141
1142 if (strcmp(buf, match->driver_data) >= 0)
1143 goto enable_64bit;
1144 else {
1145 dev_warn(&pdev->dev,
1146 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1147 match->ident);
1148 return false;
1149 }
1150
1151 enable_64bit:
1152 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1153 return true;
1154 }
1155
ahci_broken_system_poweroff(struct pci_dev * pdev)1156 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1157 {
1158 static const struct dmi_system_id broken_systems[] = {
1159 {
1160 .ident = "HP Compaq nx6310",
1161 .matches = {
1162 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1163 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1164 },
1165 /* PCI slot number of the controller */
1166 .driver_data = (void *)0x1FUL,
1167 },
1168 {
1169 .ident = "HP Compaq 6720s",
1170 .matches = {
1171 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1172 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1173 },
1174 /* PCI slot number of the controller */
1175 .driver_data = (void *)0x1FUL,
1176 },
1177
1178 { } /* terminate list */
1179 };
1180 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1181
1182 if (dmi) {
1183 unsigned long slot = (unsigned long)dmi->driver_data;
1184 /* apply the quirk only to on-board controllers */
1185 return slot == PCI_SLOT(pdev->devfn);
1186 }
1187
1188 return false;
1189 }
1190
ahci_broken_suspend(struct pci_dev * pdev)1191 static bool ahci_broken_suspend(struct pci_dev *pdev)
1192 {
1193 static const struct dmi_system_id sysids[] = {
1194 /*
1195 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1196 * to the harddisk doesn't become online after
1197 * resuming from STR. Warn and fail suspend.
1198 *
1199 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1200 *
1201 * Use dates instead of versions to match as HP is
1202 * apparently recycling both product and version
1203 * strings.
1204 *
1205 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1206 */
1207 {
1208 .ident = "dv4",
1209 .matches = {
1210 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1211 DMI_MATCH(DMI_PRODUCT_NAME,
1212 "HP Pavilion dv4 Notebook PC"),
1213 },
1214 .driver_data = "20090105", /* F.30 */
1215 },
1216 {
1217 .ident = "dv5",
1218 .matches = {
1219 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1220 DMI_MATCH(DMI_PRODUCT_NAME,
1221 "HP Pavilion dv5 Notebook PC"),
1222 },
1223 .driver_data = "20090506", /* F.16 */
1224 },
1225 {
1226 .ident = "dv6",
1227 .matches = {
1228 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1229 DMI_MATCH(DMI_PRODUCT_NAME,
1230 "HP Pavilion dv6 Notebook PC"),
1231 },
1232 .driver_data = "20090423", /* F.21 */
1233 },
1234 {
1235 .ident = "HDX18",
1236 .matches = {
1237 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1238 DMI_MATCH(DMI_PRODUCT_NAME,
1239 "HP HDX18 Notebook PC"),
1240 },
1241 .driver_data = "20090430", /* F.23 */
1242 },
1243 /*
1244 * Acer eMachines G725 has the same problem. BIOS
1245 * V1.03 is known to be broken. V3.04 is known to
1246 * work. Between, there are V1.06, V2.06 and V3.03
1247 * that we don't have much idea about. For now,
1248 * blacklist anything older than V3.04.
1249 *
1250 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1251 */
1252 {
1253 .ident = "G725",
1254 .matches = {
1255 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1256 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1257 },
1258 .driver_data = "20091216", /* V3.04 */
1259 },
1260 { } /* terminate list */
1261 };
1262 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1263 int year, month, date;
1264 char buf[9];
1265
1266 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1267 return false;
1268
1269 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1270 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1271
1272 return strcmp(buf, dmi->driver_data) < 0;
1273 }
1274
ahci_broken_lpm(struct pci_dev * pdev)1275 static bool ahci_broken_lpm(struct pci_dev *pdev)
1276 {
1277 static const struct dmi_system_id sysids[] = {
1278 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1279 {
1280 .matches = {
1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1283 },
1284 .driver_data = "20180406", /* 1.31 */
1285 },
1286 {
1287 .matches = {
1288 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1289 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1290 },
1291 .driver_data = "20180420", /* 1.28 */
1292 },
1293 {
1294 .matches = {
1295 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1296 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1297 },
1298 .driver_data = "20180315", /* 1.33 */
1299 },
1300 {
1301 .matches = {
1302 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1303 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1304 },
1305 /*
1306 * Note date based on release notes, 2.35 has been
1307 * reported to be good, but I've been unable to get
1308 * a hold of the reporter to get the DMI BIOS date.
1309 * TODO: fix this.
1310 */
1311 .driver_data = "20180310", /* 2.35 */
1312 },
1313 { } /* terminate list */
1314 };
1315 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1316 int year, month, date;
1317 char buf[9];
1318
1319 if (!dmi)
1320 return false;
1321
1322 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1323 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1324
1325 return strcmp(buf, dmi->driver_data) < 0;
1326 }
1327
ahci_broken_online(struct pci_dev * pdev)1328 static bool ahci_broken_online(struct pci_dev *pdev)
1329 {
1330 #define ENCODE_BUSDEVFN(bus, slot, func) \
1331 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1332 static const struct dmi_system_id sysids[] = {
1333 /*
1334 * There are several gigabyte boards which use
1335 * SIMG5723s configured as hardware RAID. Certain
1336 * 5723 firmware revisions shipped there keep the link
1337 * online but fail to answer properly to SRST or
1338 * IDENTIFY when no device is attached downstream
1339 * causing libata to retry quite a few times leading
1340 * to excessive detection delay.
1341 *
1342 * As these firmwares respond to the second reset try
1343 * with invalid device signature, considering unknown
1344 * sig as offline works around the problem acceptably.
1345 */
1346 {
1347 .ident = "EP45-DQ6",
1348 .matches = {
1349 DMI_MATCH(DMI_BOARD_VENDOR,
1350 "Gigabyte Technology Co., Ltd."),
1351 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1352 },
1353 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1354 },
1355 {
1356 .ident = "EP45-DS5",
1357 .matches = {
1358 DMI_MATCH(DMI_BOARD_VENDOR,
1359 "Gigabyte Technology Co., Ltd."),
1360 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1361 },
1362 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1363 },
1364 { } /* terminate list */
1365 };
1366 #undef ENCODE_BUSDEVFN
1367 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1368 unsigned int val;
1369
1370 if (!dmi)
1371 return false;
1372
1373 val = (unsigned long)dmi->driver_data;
1374
1375 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1376 }
1377
ahci_broken_devslp(struct pci_dev * pdev)1378 static bool ahci_broken_devslp(struct pci_dev *pdev)
1379 {
1380 /* device with broken DEVSLP but still showing SDS capability */
1381 static const struct pci_device_id ids[] = {
1382 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1383 {}
1384 };
1385
1386 return pci_match_id(ids, pdev);
1387 }
1388
1389 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1390 static void ahci_gtf_filter_workaround(struct ata_host *host)
1391 {
1392 static const struct dmi_system_id sysids[] = {
1393 /*
1394 * Aspire 3810T issues a bunch of SATA enable commands
1395 * via _GTF including an invalid one and one which is
1396 * rejected by the device. Among the successful ones
1397 * is FPDMA non-zero offset enable which when enabled
1398 * only on the drive side leads to NCQ command
1399 * failures. Filter it out.
1400 */
1401 {
1402 .ident = "Aspire 3810T",
1403 .matches = {
1404 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1405 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1406 },
1407 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1408 },
1409 { }
1410 };
1411 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1412 unsigned int filter;
1413 int i;
1414
1415 if (!dmi)
1416 return;
1417
1418 filter = (unsigned long)dmi->driver_data;
1419 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1420 filter, dmi->ident);
1421
1422 for (i = 0; i < host->n_ports; i++) {
1423 struct ata_port *ap = host->ports[i];
1424 struct ata_link *link;
1425 struct ata_device *dev;
1426
1427 ata_for_each_link(link, ap, EDGE)
1428 ata_for_each_dev(dev, link, ALL)
1429 dev->gtf_filter |= filter;
1430 }
1431 }
1432 #else
ahci_gtf_filter_workaround(struct ata_host * host)1433 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1434 {}
1435 #endif
1436
1437 /*
1438 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1439 * as DUMMY, or detected but eventually get a "link down" and never get up
1440 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1441 * port_map may hold a value of 0x00.
1442 *
1443 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1444 * and can significantly reduce the occurrence of the problem.
1445 *
1446 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1447 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1448 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1449 struct pci_dev *pdev)
1450 {
1451 static const struct dmi_system_id sysids[] = {
1452 {
1453 .ident = "Acer Switch Alpha 12",
1454 .matches = {
1455 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1456 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1457 },
1458 },
1459 { }
1460 };
1461
1462 if (dmi_check_system(sysids)) {
1463 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1464 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1465 hpriv->port_map = 0x7;
1466 hpriv->cap = 0xC734FF02;
1467 }
1468 }
1469 }
1470
1471 #ifdef CONFIG_ARM64
1472 /*
1473 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1474 * Workaround is to make sure all pending IRQs are served before leaving
1475 * handler.
1476 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1477 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1478 {
1479 struct ata_host *host = dev_instance;
1480 struct ahci_host_priv *hpriv;
1481 unsigned int rc = 0;
1482 void __iomem *mmio;
1483 u32 irq_stat, irq_masked;
1484 unsigned int handled = 1;
1485
1486 VPRINTK("ENTER\n");
1487 hpriv = host->private_data;
1488 mmio = hpriv->mmio;
1489 irq_stat = readl(mmio + HOST_IRQ_STAT);
1490 if (!irq_stat)
1491 return IRQ_NONE;
1492
1493 do {
1494 irq_masked = irq_stat & hpriv->port_map;
1495 spin_lock(&host->lock);
1496 rc = ahci_handle_port_intr(host, irq_masked);
1497 if (!rc)
1498 handled = 0;
1499 writel(irq_stat, mmio + HOST_IRQ_STAT);
1500 irq_stat = readl(mmio + HOST_IRQ_STAT);
1501 spin_unlock(&host->lock);
1502 } while (irq_stat);
1503 VPRINTK("EXIT\n");
1504
1505 return IRQ_RETVAL(handled);
1506 }
1507 #endif
1508
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1509 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1510 struct ahci_host_priv *hpriv)
1511 {
1512 int i, count = 0;
1513 u32 cap;
1514
1515 /*
1516 * Check if this device might have remapped nvme devices.
1517 */
1518 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1519 pci_resource_len(pdev, bar) < SZ_512K ||
1520 bar != AHCI_PCI_BAR_STANDARD ||
1521 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1522 return;
1523
1524 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1525 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1526 if ((cap & (1 << i)) == 0)
1527 continue;
1528 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1529 != PCI_CLASS_STORAGE_EXPRESS)
1530 continue;
1531
1532 /* We've found a remapped device */
1533 count++;
1534 }
1535
1536 if (!count)
1537 return;
1538
1539 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1540 dev_warn(&pdev->dev,
1541 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1542
1543 /*
1544 * Don't rely on the msi-x capability in the remap case,
1545 * share the legacy interrupt across ahci and remapped devices.
1546 */
1547 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1548 }
1549
ahci_get_irq_vector(struct ata_host * host,int port)1550 static int ahci_get_irq_vector(struct ata_host *host, int port)
1551 {
1552 return pci_irq_vector(to_pci_dev(host->dev), port);
1553 }
1554
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1555 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1556 struct ahci_host_priv *hpriv)
1557 {
1558 int nvec;
1559
1560 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1561 return -ENODEV;
1562
1563 /*
1564 * If number of MSIs is less than number of ports then Sharing Last
1565 * Message mode could be enforced. In this case assume that advantage
1566 * of multipe MSIs is negated and use single MSI mode instead.
1567 */
1568 if (n_ports > 1) {
1569 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1570 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1571 if (nvec > 0) {
1572 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1573 hpriv->get_irq_vector = ahci_get_irq_vector;
1574 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1575 return nvec;
1576 }
1577
1578 /*
1579 * Fallback to single MSI mode if the controller
1580 * enforced MRSM mode.
1581 */
1582 printk(KERN_INFO
1583 "ahci: MRSM is on, fallback to single MSI\n");
1584 pci_free_irq_vectors(pdev);
1585 }
1586 }
1587
1588 /*
1589 * If the host is not capable of supporting per-port vectors, fall
1590 * back to single MSI before finally attempting single MSI-X.
1591 */
1592 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1593 if (nvec == 1)
1594 return nvec;
1595 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1596 }
1597
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1598 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1599 struct ahci_host_priv *hpriv)
1600 {
1601 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1602
1603
1604 /* Ignore processing for non mobile platforms */
1605 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1606 return;
1607
1608 /* user modified policy via module param */
1609 if (mobile_lpm_policy != -1) {
1610 policy = mobile_lpm_policy;
1611 goto update_policy;
1612 }
1613
1614 #ifdef CONFIG_ACPI
1615 if (policy > ATA_LPM_MED_POWER &&
1616 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1617 if (hpriv->cap & HOST_CAP_PART)
1618 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1619 else if (hpriv->cap & HOST_CAP_SSC)
1620 policy = ATA_LPM_MIN_POWER;
1621 }
1622 #endif
1623
1624 update_policy:
1625 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1626 ap->target_lpm_policy = policy;
1627 }
1628
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1629 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1630 {
1631 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1632 u16 tmp16;
1633
1634 /*
1635 * Only apply the 6-port PCS quirk for known legacy platforms.
1636 */
1637 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1638 return;
1639
1640 /* Skip applying the quirk on Denverton and beyond */
1641 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1642 return;
1643
1644 /*
1645 * port_map is determined from PORTS_IMPL PCI register which is
1646 * implemented as write or write-once register. If the register
1647 * isn't programmed, ahci automatically generates it from number
1648 * of ports, which is good enough for PCS programming. It is
1649 * otherwise expected that platform firmware enables the ports
1650 * before the OS boots.
1651 */
1652 pci_read_config_word(pdev, PCS_6, &tmp16);
1653 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1654 tmp16 |= hpriv->port_map;
1655 pci_write_config_word(pdev, PCS_6, tmp16);
1656 }
1657 }
1658
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1659 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1660 {
1661 unsigned int board_id = ent->driver_data;
1662 struct ata_port_info pi = ahci_port_info[board_id];
1663 const struct ata_port_info *ppi[] = { &pi, NULL };
1664 struct device *dev = &pdev->dev;
1665 struct ahci_host_priv *hpriv;
1666 struct ata_host *host;
1667 int n_ports, i, rc;
1668 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1669
1670 VPRINTK("ENTER\n");
1671
1672 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1673
1674 ata_print_version_once(&pdev->dev, DRV_VERSION);
1675
1676 /* The AHCI driver can only drive the SATA ports, the PATA driver
1677 can drive them all so if both drivers are selected make sure
1678 AHCI stays out of the way */
1679 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1680 return -ENODEV;
1681
1682 /* Apple BIOS on MCP89 prevents us using AHCI */
1683 if (is_mcp89_apple(pdev))
1684 ahci_mcp89_apple_enable(pdev);
1685
1686 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1687 * At the moment, we can only use the AHCI mode. Let the users know
1688 * that for SAS drives they're out of luck.
1689 */
1690 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1691 dev_info(&pdev->dev,
1692 "PDC42819 can only drive SATA devices with this driver\n");
1693
1694 /* Some devices use non-standard BARs */
1695 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1696 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1697 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1698 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1699 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1700 if (pdev->device == 0xa01c)
1701 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1702 if (pdev->device == 0xa084)
1703 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1704 }
1705
1706 /* acquire resources */
1707 rc = pcim_enable_device(pdev);
1708 if (rc)
1709 return rc;
1710
1711 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1712 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1713 u8 map;
1714
1715 /* ICH6s share the same PCI ID for both piix and ahci
1716 * modes. Enabling ahci mode while MAP indicates
1717 * combined mode is a bad idea. Yield to ata_piix.
1718 */
1719 pci_read_config_byte(pdev, ICH_MAP, &map);
1720 if (map & 0x3) {
1721 dev_info(&pdev->dev,
1722 "controller is in combined mode, can't enable AHCI mode\n");
1723 return -ENODEV;
1724 }
1725 }
1726
1727 /* AHCI controllers often implement SFF compatible interface.
1728 * Grab all PCI BARs just in case.
1729 */
1730 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1731 if (rc == -EBUSY)
1732 pcim_pin_device(pdev);
1733 if (rc)
1734 return rc;
1735
1736 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1737 if (!hpriv)
1738 return -ENOMEM;
1739 hpriv->flags |= (unsigned long)pi.private_data;
1740
1741 /* MCP65 revision A1 and A2 can't do MSI */
1742 if (board_id == board_ahci_mcp65 &&
1743 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1744 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1745
1746 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1747 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1748 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1749
1750 /* only some SB600s can do 64bit DMA */
1751 if (ahci_sb600_enable_64bit(pdev))
1752 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1753
1754 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1755
1756 /* detect remapped nvme devices */
1757 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1758
1759 /* must set flag prior to save config in order to take effect */
1760 if (ahci_broken_devslp(pdev))
1761 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1762
1763 #ifdef CONFIG_ARM64
1764 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1765 hpriv->irq_handler = ahci_thunderx_irq_handler;
1766 #endif
1767
1768 /* save initial config */
1769 ahci_pci_save_initial_config(pdev, hpriv);
1770
1771 /*
1772 * If platform firmware failed to enable ports, try to enable
1773 * them here.
1774 */
1775 ahci_intel_pcs_quirk(pdev, hpriv);
1776
1777 /* prepare host */
1778 if (hpriv->cap & HOST_CAP_NCQ) {
1779 pi.flags |= ATA_FLAG_NCQ;
1780 /*
1781 * Auto-activate optimization is supposed to be
1782 * supported on all AHCI controllers indicating NCQ
1783 * capability, but it seems to be broken on some
1784 * chipsets including NVIDIAs.
1785 */
1786 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1787 pi.flags |= ATA_FLAG_FPDMA_AA;
1788
1789 /*
1790 * All AHCI controllers should be forward-compatible
1791 * with the new auxiliary field. This code should be
1792 * conditionalized if any buggy AHCI controllers are
1793 * encountered.
1794 */
1795 pi.flags |= ATA_FLAG_FPDMA_AUX;
1796 }
1797
1798 if (hpriv->cap & HOST_CAP_PMP)
1799 pi.flags |= ATA_FLAG_PMP;
1800
1801 ahci_set_em_messages(hpriv, &pi);
1802
1803 if (ahci_broken_system_poweroff(pdev)) {
1804 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1805 dev_info(&pdev->dev,
1806 "quirky BIOS, skipping spindown on poweroff\n");
1807 }
1808
1809 if (ahci_broken_lpm(pdev)) {
1810 pi.flags |= ATA_FLAG_NO_LPM;
1811 dev_warn(&pdev->dev,
1812 "BIOS update required for Link Power Management support\n");
1813 }
1814
1815 if (ahci_broken_suspend(pdev)) {
1816 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1817 dev_warn(&pdev->dev,
1818 "BIOS update required for suspend/resume\n");
1819 }
1820
1821 if (ahci_broken_online(pdev)) {
1822 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1823 dev_info(&pdev->dev,
1824 "online status unreliable, applying workaround\n");
1825 }
1826
1827
1828 /* Acer SA5-271 workaround modifies private_data */
1829 acer_sa5_271_workaround(hpriv, pdev);
1830
1831 /* CAP.NP sometimes indicate the index of the last enabled
1832 * port, at other times, that of the last possible port, so
1833 * determining the maximum port number requires looking at
1834 * both CAP.NP and port_map.
1835 */
1836 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1837
1838 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1839 if (!host)
1840 return -ENOMEM;
1841 host->private_data = hpriv;
1842
1843 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1844 /* legacy intx interrupts */
1845 pci_intx(pdev, 1);
1846 }
1847 hpriv->irq = pci_irq_vector(pdev, 0);
1848
1849 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1850 host->flags |= ATA_HOST_PARALLEL_SCAN;
1851 else
1852 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1853
1854 if (pi.flags & ATA_FLAG_EM)
1855 ahci_reset_em(host);
1856
1857 for (i = 0; i < host->n_ports; i++) {
1858 struct ata_port *ap = host->ports[i];
1859
1860 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1861 ata_port_pbar_desc(ap, ahci_pci_bar,
1862 0x100 + ap->port_no * 0x80, "port");
1863
1864 /* set enclosure management message type */
1865 if (ap->flags & ATA_FLAG_EM)
1866 ap->em_message_type = hpriv->em_msg_type;
1867
1868 ahci_update_initial_lpm_policy(ap, hpriv);
1869
1870 /* disabled/not-implemented port */
1871 if (!(hpriv->port_map & (1 << i)))
1872 ap->ops = &ata_dummy_port_ops;
1873 }
1874
1875 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1876 ahci_p5wdh_workaround(host);
1877
1878 /* apply gtf filter quirk */
1879 ahci_gtf_filter_workaround(host);
1880
1881 /* initialize adapter */
1882 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1883 if (rc)
1884 return rc;
1885
1886 rc = ahci_reset_controller(host);
1887 if (rc)
1888 return rc;
1889
1890 ahci_pci_init_controller(host);
1891 ahci_pci_print_info(host);
1892
1893 pci_set_master(pdev);
1894
1895 rc = ahci_host_activate(host, &ahci_sht);
1896 if (rc)
1897 return rc;
1898
1899 pm_runtime_put_noidle(&pdev->dev);
1900 return 0;
1901 }
1902
ahci_shutdown_one(struct pci_dev * pdev)1903 static void ahci_shutdown_one(struct pci_dev *pdev)
1904 {
1905 ata_pci_shutdown_one(pdev);
1906 }
1907
ahci_remove_one(struct pci_dev * pdev)1908 static void ahci_remove_one(struct pci_dev *pdev)
1909 {
1910 pm_runtime_get_noresume(&pdev->dev);
1911 ata_pci_remove_one(pdev);
1912 }
1913
1914 module_pci_driver(ahci_pci_driver);
1915
1916 MODULE_AUTHOR("Jeff Garzik");
1917 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1918 MODULE_LICENSE("GPL");
1919 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1920 MODULE_VERSION(DRV_VERSION);
1921