1 /*
2 * Broadcom SATA3 AHCI Controller Driver
3 *
4 * Copyright © 2009-2015 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/ahci_platform.h>
18 #include <linux/compiler.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/libata.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/platform_device.h>
28 #include <linux/reset.h>
29 #include <linux/string.h>
30
31 #include "ahci.h"
32
33 #define DRV_NAME "brcm-ahci"
34
35 #define SATA_TOP_CTRL_VERSION 0x0
36 #define SATA_TOP_CTRL_BUS_CTRL 0x4
37 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
38 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
39 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
40 #define PIODATA_ENDIAN_SHIFT 6
41 #define ENDIAN_SWAP_NONE 0
42 #define ENDIAN_SWAP_FULL 2
43 #define SATA_TOP_CTRL_TP_CTRL 0x8
44 #define SATA_TOP_CTRL_PHY_CTRL 0xc
45 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0
46 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
47 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4
48 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
49 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
50 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
51 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
52 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
53 #define SATA_TOP_CTRL_PHY_OFFS 0x8
54 #define SATA_TOP_MAX_PHYS 2
55
56 #define SATA_FIRST_PORT_CTRL 0x700
57 #define SATA_NEXT_PORT_CTRL_OFFSET 0x80
58 #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
59
60 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
61 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
62 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
63 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
64 #else
65 #define DATA_ENDIAN 0
66 #define MMIO_ENDIAN 0
67 #endif
68
69 #define BUS_CTRL_ENDIAN_CONF \
70 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \
71 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
72 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
73
74 #define BUS_CTRL_ENDIAN_NSP_CONF \
75 (0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)
76
77 #define BUS_CTRL_ENDIAN_CONF_MASK \
78 (0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT | \
79 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)
80
81 enum brcm_ahci_version {
82 BRCM_SATA_BCM7425 = 1,
83 BRCM_SATA_BCM7445,
84 BRCM_SATA_NSP,
85 };
86
87 enum brcm_ahci_quirks {
88 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0),
89 };
90
91 struct brcm_ahci_priv {
92 struct device *dev;
93 void __iomem *top_ctrl;
94 u32 port_mask;
95 u32 quirks;
96 enum brcm_ahci_version version;
97 struct reset_control *rcdev;
98 };
99
brcm_sata_readreg(void __iomem * addr)100 static inline u32 brcm_sata_readreg(void __iomem *addr)
101 {
102 /*
103 * MIPS endianness is configured by boot strap, which also reverses all
104 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
105 * endian I/O).
106 *
107 * Other architectures (e.g., ARM) either do not support big endian, or
108 * else leave I/O in little endian mode.
109 */
110 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
111 return __raw_readl(addr);
112 else
113 return readl_relaxed(addr);
114 }
115
brcm_sata_writereg(u32 val,void __iomem * addr)116 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
117 {
118 /* See brcm_sata_readreg() comments */
119 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
120 __raw_writel(val, addr);
121 else
122 writel_relaxed(val, addr);
123 }
124
brcm_sata_alpm_init(struct ahci_host_priv * hpriv)125 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
126 {
127 struct brcm_ahci_priv *priv = hpriv->plat_data;
128 u32 port_ctrl, host_caps;
129 int i;
130
131 /* Enable support for ALPM */
132 host_caps = readl(hpriv->mmio + HOST_CAP);
133 if (!(host_caps & HOST_CAP_ALPM))
134 hpriv->flags |= AHCI_HFLAG_YES_ALPM;
135
136 /*
137 * Adjust timeout to allow PLL sufficient time to lock while waking
138 * up from slumber mode.
139 */
140 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
141 i < SATA_TOP_MAX_PHYS;
142 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
143 if (priv->port_mask & BIT(i))
144 writel(0xff1003fc,
145 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
146 }
147 }
148
brcm_sata_phy_enable(struct brcm_ahci_priv * priv,int port)149 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
150 {
151 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
152 (port * SATA_TOP_CTRL_PHY_OFFS);
153 void __iomem *p;
154 u32 reg;
155
156 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
157 return;
158
159 /* clear PHY_DEFAULT_POWER_STATE */
160 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
161 reg = brcm_sata_readreg(p);
162 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
163 brcm_sata_writereg(reg, p);
164
165 /* reset the PHY digital logic */
166 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
167 reg = brcm_sata_readreg(p);
168 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
169 SATA_TOP_CTRL_2_SW_RST_RX);
170 reg |= SATA_TOP_CTRL_2_SW_RST_TX;
171 brcm_sata_writereg(reg, p);
172 reg = brcm_sata_readreg(p);
173 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
174 brcm_sata_writereg(reg, p);
175 reg = brcm_sata_readreg(p);
176 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
177 brcm_sata_writereg(reg, p);
178 (void)brcm_sata_readreg(p);
179 }
180
brcm_sata_phy_disable(struct brcm_ahci_priv * priv,int port)181 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
182 {
183 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
184 (port * SATA_TOP_CTRL_PHY_OFFS);
185 void __iomem *p;
186 u32 reg;
187
188 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
189 return;
190
191 /* power-off the PHY digital logic */
192 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
193 reg = brcm_sata_readreg(p);
194 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
195 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
196 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
197 brcm_sata_writereg(reg, p);
198
199 /* set PHY_DEFAULT_POWER_STATE */
200 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
201 reg = brcm_sata_readreg(p);
202 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
203 brcm_sata_writereg(reg, p);
204 }
205
brcm_sata_phys_enable(struct brcm_ahci_priv * priv)206 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
207 {
208 int i;
209
210 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
211 if (priv->port_mask & BIT(i))
212 brcm_sata_phy_enable(priv, i);
213 }
214
brcm_sata_phys_disable(struct brcm_ahci_priv * priv)215 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
216 {
217 int i;
218
219 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
220 if (priv->port_mask & BIT(i))
221 brcm_sata_phy_disable(priv, i);
222 }
223
brcm_ahci_get_portmask(struct ahci_host_priv * hpriv,struct brcm_ahci_priv * priv)224 static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
225 struct brcm_ahci_priv *priv)
226 {
227 u32 impl;
228
229 impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
230
231 if (fls(impl) > SATA_TOP_MAX_PHYS)
232 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
233 impl);
234 else if (!impl)
235 dev_info(priv->dev, "no ports found\n");
236
237 return impl;
238 }
239
brcm_sata_init(struct brcm_ahci_priv * priv)240 static void brcm_sata_init(struct brcm_ahci_priv *priv)
241 {
242 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
243 u32 data;
244
245 /* Configure endianness */
246 data = brcm_sata_readreg(ctrl);
247 data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
248 if (priv->version == BRCM_SATA_NSP)
249 data |= BUS_CTRL_ENDIAN_NSP_CONF;
250 else
251 data |= BUS_CTRL_ENDIAN_CONF;
252 brcm_sata_writereg(data, ctrl);
253 }
254
brcm_ahci_read_id(struct ata_device * dev,struct ata_taskfile * tf,u16 * id)255 static unsigned int brcm_ahci_read_id(struct ata_device *dev,
256 struct ata_taskfile *tf, u16 *id)
257 {
258 struct ata_port *ap = dev->link->ap;
259 struct ata_host *host = ap->host;
260 struct ahci_host_priv *hpriv = host->private_data;
261 struct brcm_ahci_priv *priv = hpriv->plat_data;
262 void __iomem *mmio = hpriv->mmio;
263 unsigned int err_mask;
264 unsigned long flags;
265 int i, rc;
266 u32 ctl;
267
268 /* Try to read the device ID and, if this fails, proceed with the
269 * recovery sequence below
270 */
271 err_mask = ata_do_dev_read_id(dev, tf, id);
272 if (likely(!err_mask))
273 return err_mask;
274
275 /* Disable host interrupts */
276 spin_lock_irqsave(&host->lock, flags);
277 ctl = readl(mmio + HOST_CTL);
278 ctl &= ~HOST_IRQ_EN;
279 writel(ctl, mmio + HOST_CTL);
280 readl(mmio + HOST_CTL); /* flush */
281 spin_unlock_irqrestore(&host->lock, flags);
282
283 /* Perform the SATA PHY reset sequence */
284 brcm_sata_phy_disable(priv, ap->port_no);
285
286 /* Reset the SATA clock */
287 ahci_platform_disable_clks(hpriv);
288 msleep(10);
289
290 ahci_platform_enable_clks(hpriv);
291 msleep(10);
292
293 /* Bring the PHY back on */
294 brcm_sata_phy_enable(priv, ap->port_no);
295
296 /* Re-initialize and calibrate the PHY */
297 for (i = 0; i < hpriv->nports; i++) {
298 rc = phy_init(hpriv->phys[i]);
299 if (rc)
300 goto disable_phys;
301
302 rc = phy_calibrate(hpriv->phys[i]);
303 if (rc) {
304 phy_exit(hpriv->phys[i]);
305 goto disable_phys;
306 }
307 }
308
309 /* Re-enable host interrupts */
310 spin_lock_irqsave(&host->lock, flags);
311 ctl = readl(mmio + HOST_CTL);
312 ctl |= HOST_IRQ_EN;
313 writel(ctl, mmio + HOST_CTL);
314 readl(mmio + HOST_CTL); /* flush */
315 spin_unlock_irqrestore(&host->lock, flags);
316
317 return ata_do_dev_read_id(dev, tf, id);
318
319 disable_phys:
320 while (--i >= 0) {
321 phy_power_off(hpriv->phys[i]);
322 phy_exit(hpriv->phys[i]);
323 }
324
325 return AC_ERR_OTHER;
326 }
327
brcm_ahci_host_stop(struct ata_host * host)328 static void brcm_ahci_host_stop(struct ata_host *host)
329 {
330 struct ahci_host_priv *hpriv = host->private_data;
331
332 ahci_platform_disable_resources(hpriv);
333 }
334
335 static struct ata_port_operations ahci_brcm_platform_ops = {
336 .inherits = &ahci_ops,
337 .host_stop = brcm_ahci_host_stop,
338 .read_id = brcm_ahci_read_id,
339 };
340
341 static const struct ata_port_info ahci_brcm_port_info = {
342 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
343 .link_flags = ATA_LFLAG_NO_DB_DELAY,
344 .pio_mask = ATA_PIO4,
345 .udma_mask = ATA_UDMA6,
346 .port_ops = &ahci_brcm_platform_ops,
347 };
348
349 #ifdef CONFIG_PM_SLEEP
brcm_ahci_suspend(struct device * dev)350 static int brcm_ahci_suspend(struct device *dev)
351 {
352 struct ata_host *host = dev_get_drvdata(dev);
353 struct ahci_host_priv *hpriv = host->private_data;
354 struct brcm_ahci_priv *priv = hpriv->plat_data;
355
356 brcm_sata_phys_disable(priv);
357
358 return ahci_platform_suspend(dev);
359 }
360
brcm_ahci_resume(struct device * dev)361 static int brcm_ahci_resume(struct device *dev)
362 {
363 struct ata_host *host = dev_get_drvdata(dev);
364 struct ahci_host_priv *hpriv = host->private_data;
365 struct brcm_ahci_priv *priv = hpriv->plat_data;
366 int ret;
367
368 /* Make sure clocks are turned on before re-configuration */
369 ret = ahci_platform_enable_clks(hpriv);
370 if (ret)
371 return ret;
372
373 brcm_sata_init(priv);
374 brcm_sata_phys_enable(priv);
375 brcm_sata_alpm_init(hpriv);
376
377 /* Since we had to enable clocks earlier on, we cannot use
378 * ahci_platform_resume() as-is since a second call to
379 * ahci_platform_enable_resources() would bump up the resources
380 * (regulators, clocks, PHYs) count artificially so we copy the part
381 * after ahci_platform_enable_resources().
382 */
383 ret = ahci_platform_enable_phys(hpriv);
384 if (ret)
385 goto out_disable_phys;
386
387 ret = ahci_platform_resume_host(dev);
388 if (ret)
389 goto out_disable_platform_phys;
390
391 /* We resumed so update PM runtime state */
392 pm_runtime_disable(dev);
393 pm_runtime_set_active(dev);
394 pm_runtime_enable(dev);
395
396 return 0;
397
398 out_disable_platform_phys:
399 ahci_platform_disable_phys(hpriv);
400 out_disable_phys:
401 brcm_sata_phys_disable(priv);
402 ahci_platform_disable_clks(hpriv);
403 return ret;
404 }
405 #endif
406
407 static struct scsi_host_template ahci_platform_sht = {
408 AHCI_SHT(DRV_NAME),
409 };
410
411 static const struct of_device_id ahci_of_match[] = {
412 {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
413 {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
414 {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
415 {},
416 };
417 MODULE_DEVICE_TABLE(of, ahci_of_match);
418
brcm_ahci_probe(struct platform_device * pdev)419 static int brcm_ahci_probe(struct platform_device *pdev)
420 {
421 const struct of_device_id *of_id;
422 struct device *dev = &pdev->dev;
423 struct brcm_ahci_priv *priv;
424 struct ahci_host_priv *hpriv;
425 struct resource *res;
426 int ret;
427
428 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
429 if (!priv)
430 return -ENOMEM;
431
432 of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
433 if (!of_id)
434 return -ENODEV;
435
436 priv->version = (enum brcm_ahci_version)of_id->data;
437 priv->dev = dev;
438
439 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
440 priv->top_ctrl = devm_ioremap_resource(dev, res);
441 if (IS_ERR(priv->top_ctrl))
442 return PTR_ERR(priv->top_ctrl);
443
444 /* Reset is optional depending on platform */
445 priv->rcdev = devm_reset_control_get(&pdev->dev, "ahci");
446 if (!IS_ERR_OR_NULL(priv->rcdev))
447 reset_control_deassert(priv->rcdev);
448
449 hpriv = ahci_platform_get_resources(pdev, 0);
450 if (IS_ERR(hpriv)) {
451 ret = PTR_ERR(hpriv);
452 goto out_reset;
453 }
454
455 hpriv->plat_data = priv;
456 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO;
457
458 switch (priv->version) {
459 case BRCM_SATA_BCM7425:
460 hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
461 /* fall through */
462 case BRCM_SATA_NSP:
463 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
464 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
465 break;
466 default:
467 break;
468 }
469
470 ret = ahci_platform_enable_clks(hpriv);
471 if (ret)
472 goto out_reset;
473
474 /* Must be first so as to configure endianness including that
475 * of the standard AHCI register space.
476 */
477 brcm_sata_init(priv);
478
479 /* Initializes priv->port_mask which is used below */
480 priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
481 if (!priv->port_mask) {
482 ret = -ENODEV;
483 goto out_disable_clks;
484 }
485
486 /* Must be done before ahci_platform_enable_phys() */
487 brcm_sata_phys_enable(priv);
488
489 brcm_sata_alpm_init(hpriv);
490
491 ret = ahci_platform_enable_phys(hpriv);
492 if (ret)
493 goto out_disable_phys;
494
495 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
496 &ahci_platform_sht);
497 if (ret)
498 goto out_disable_platform_phys;
499
500 dev_info(dev, "Broadcom AHCI SATA3 registered\n");
501
502 return 0;
503
504 out_disable_platform_phys:
505 ahci_platform_disable_phys(hpriv);
506 out_disable_phys:
507 brcm_sata_phys_disable(priv);
508 out_disable_clks:
509 ahci_platform_disable_clks(hpriv);
510 out_reset:
511 if (!IS_ERR_OR_NULL(priv->rcdev))
512 reset_control_assert(priv->rcdev);
513 return ret;
514 }
515
brcm_ahci_remove(struct platform_device * pdev)516 static int brcm_ahci_remove(struct platform_device *pdev)
517 {
518 struct ata_host *host = dev_get_drvdata(&pdev->dev);
519 struct ahci_host_priv *hpriv = host->private_data;
520 struct brcm_ahci_priv *priv = hpriv->plat_data;
521 int ret;
522
523 brcm_sata_phys_disable(priv);
524
525 ret = ata_platform_remove_one(pdev);
526 if (ret)
527 return ret;
528
529 return 0;
530 }
531
532 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
533
534 static struct platform_driver brcm_ahci_driver = {
535 .probe = brcm_ahci_probe,
536 .remove = brcm_ahci_remove,
537 .driver = {
538 .name = DRV_NAME,
539 .of_match_table = ahci_of_match,
540 .pm = &ahci_brcm_pm_ops,
541 },
542 };
543 module_platform_driver(brcm_ahci_driver);
544
545 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
546 MODULE_AUTHOR("Brian Norris");
547 MODULE_LICENSE("GPL");
548 MODULE_ALIAS("platform:sata-brcmstb");
549