1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/nospec.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include <linux/pci.h>
48 #include "ahci.h"
49 #include "libata.h"
50
51 static int ahci_skip_host_reset;
52 int ahci_ignore_sss;
53 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54
55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57
58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60
61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 unsigned hints);
63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 size_t size);
66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
67 ssize_t size);
68
69
70
71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
94 #ifdef CONFIG_PM
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 #endif
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
101
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
118
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
135 &dev_attr_em_buffer,
136 &dev_attr_em_message_supported,
137 NULL
138 };
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
144 &dev_attr_ncq_prio_enable,
145 NULL
146 };
147 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148
149 struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
151
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
156
157 .freeze = ahci_freeze,
158 .thaw = ahci_thaw,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
166
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
171
172 .set_lpm = ahci_set_lpm,
173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
177 .transmit_led_message = ahci_transmit_led_message,
178 #ifdef CONFIG_PM
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
181 #endif
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
184 };
185 EXPORT_SYMBOL_GPL(ahci_ops);
186
187 struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
190 };
191 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192
193 static bool ahci_em_messages __read_mostly = true;
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
198
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203
ahci_enable_ahci(void __iomem * mmio)204 static void ahci_enable_ahci(void __iomem *mmio)
205 {
206 int i;
207 u32 tmp;
208
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
212 return;
213
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
216 */
217 for (i = 0; i < 5; i++) {
218 tmp |= HOST_AHCI_EN;
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
222 return;
223 msleep(10);
224 }
225
226 WARN_ON(1);
227 }
228
229 /**
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
232 *
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
236 */
ahci_rpm_get_port(struct ata_port * ap)237 static int ahci_rpm_get_port(struct ata_port *ap)
238 {
239 return pm_runtime_get_sync(ap->dev);
240 }
241
242 /**
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
245 *
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
248 */
ahci_rpm_put_port(struct ata_port * ap)249 static void ahci_rpm_put_port(struct ata_port *ap)
250 {
251 pm_runtime_put(ap->dev);
252 }
253
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)254 static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
256 {
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
260
261 return sprintf(buf, "%x\n", hpriv->cap);
262 }
263
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
266 {
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
270
271 return sprintf(buf, "%x\n", hpriv->cap2);
272 }
273
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)274 static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
276 {
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
280
281 return sprintf(buf, "%x\n", hpriv->version);
282 }
283
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
286 {
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
290 ssize_t ret;
291
292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
295
296 return ret;
297 }
298
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
301 {
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
307 u32 em_ctl, msg;
308 unsigned long flags;
309 size_t count;
310 int i;
311
312 ahci_rpm_get_port(ap);
313 spin_lock_irqsave(ap->lock, flags);
314
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
319 ahci_rpm_put_port(ap);
320 return -EINVAL;
321 }
322
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
326 return -EAGAIN;
327 }
328
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
331
332 count = hpriv->em_buf_sz;
333
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
337 ata_port_warn(ap,
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
341 count = PAGE_SIZE;
342 }
343
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
346 buf[i] = msg & 0xff;
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
350 }
351
352 spin_unlock_irqrestore(ap->lock, flags);
353 ahci_rpm_put_port(ap);
354
355 return i;
356 }
357
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
361 {
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
367 const unsigned char *msg_buf = buf;
368 u32 em_ctl, msg;
369 unsigned long flags;
370 int i;
371
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
376 return -EINVAL;
377
378 ahci_rpm_get_port(ap);
379 spin_lock_irqsave(ap->lock, flags);
380
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
384 ahci_rpm_put_port(ap);
385 return -EBUSY;
386 }
387
388 for (i = 0; i < size; i += 4) {
389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 writel(msg, em_mmio + i);
392 }
393
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
395
396 spin_unlock_irqrestore(ap->lock, flags);
397 ahci_rpm_put_port(ap);
398
399 return size;
400 }
401
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)402 static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
404 {
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
409 u32 em_ctl;
410
411 ahci_rpm_get_port(ap);
412 em_ctl = readl(mmio + HOST_EM_CTL);
413 ahci_rpm_put_port(ap);
414
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
420 }
421
422 /**
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
426 *
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
431 *
432 * If inconsistent, config values are fixed up by this function.
433 *
434 * If it is not set already this function sets hpriv->start_engine to
435 * ahci_start_engine.
436 *
437 * LOCKING:
438 * None.
439 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
441 {
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
444 int i;
445
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
448
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
451 */
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
454
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
460 else
461 hpriv->saved_cap2 = cap2 = 0;
462
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
466 cap &= ~HOST_CAP_64;
467 }
468
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap &= ~HOST_CAP_NCQ;
472 }
473
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
476 cap |= HOST_CAP_NCQ;
477 }
478
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 cap &= ~HOST_CAP_PMP;
482 }
483
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
485 dev_info(dev,
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap &= ~HOST_CAP_SNTF;
488 }
489
490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
491 dev_info(dev,
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
495 }
496
497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
499 cap |= HOST_CAP_FBS;
500 }
501
502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
505 }
506
507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap |= HOST_CAP_ALPM;
510 }
511
512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
514 port_map, hpriv->force_port_map);
515 port_map = hpriv->force_port_map;
516 hpriv->saved_port_map = port_map;
517 }
518
519 if (hpriv->mask_port_map) {
520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
521 port_map,
522 port_map & hpriv->mask_port_map);
523 port_map &= hpriv->mask_port_map;
524 }
525
526 /* cross check port_map and cap.n_ports */
527 if (port_map) {
528 int map_ports = 0;
529
530 for (i = 0; i < AHCI_MAX_PORTS; i++)
531 if (port_map & (1 << i))
532 map_ports++;
533
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
536 */
537 if (map_ports > ahci_nr_ports(cap)) {
538 dev_warn(dev,
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map, ahci_nr_ports(cap));
541 port_map = 0;
542 }
543 }
544
545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map && vers < 0x10300) {
547 port_map = (1 << ahci_nr_ports(cap)) - 1;
548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
549
550 /* write the fixed up value to the PI register */
551 hpriv->saved_port_map = port_map;
552 }
553
554 /* record values to use during operation */
555 hpriv->cap = cap;
556 hpriv->cap2 = cap2;
557 hpriv->version = readl(mmio + HOST_VERSION);
558 hpriv->port_map = port_map;
559
560 if (!hpriv->start_engine)
561 hpriv->start_engine = ahci_start_engine;
562
563 if (!hpriv->stop_engine)
564 hpriv->stop_engine = ahci_stop_engine;
565
566 if (!hpriv->irq_handler)
567 hpriv->irq_handler = ahci_single_level_irq_intr;
568 }
569 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
570
571 /**
572 * ahci_restore_initial_config - Restore initial config
573 * @host: target ATA host
574 *
575 * Restore initial config stored by ahci_save_initial_config().
576 *
577 * LOCKING:
578 * None.
579 */
ahci_restore_initial_config(struct ata_host * host)580 static void ahci_restore_initial_config(struct ata_host *host)
581 {
582 struct ahci_host_priv *hpriv = host->private_data;
583 void __iomem *mmio = hpriv->mmio;
584
585 writel(hpriv->saved_cap, mmio + HOST_CAP);
586 if (hpriv->saved_cap2)
587 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
588 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
589 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
590 }
591
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)592 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
593 {
594 static const int offset[] = {
595 [SCR_STATUS] = PORT_SCR_STAT,
596 [SCR_CONTROL] = PORT_SCR_CTL,
597 [SCR_ERROR] = PORT_SCR_ERR,
598 [SCR_ACTIVE] = PORT_SCR_ACT,
599 [SCR_NOTIFICATION] = PORT_SCR_NTF,
600 };
601 struct ahci_host_priv *hpriv = ap->host->private_data;
602
603 if (sc_reg < ARRAY_SIZE(offset) &&
604 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
605 return offset[sc_reg];
606 return 0;
607 }
608
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)609 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
610 {
611 void __iomem *port_mmio = ahci_port_base(link->ap);
612 int offset = ahci_scr_offset(link->ap, sc_reg);
613
614 if (offset) {
615 *val = readl(port_mmio + offset);
616 return 0;
617 }
618 return -EINVAL;
619 }
620
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)621 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
622 {
623 void __iomem *port_mmio = ahci_port_base(link->ap);
624 int offset = ahci_scr_offset(link->ap, sc_reg);
625
626 if (offset) {
627 writel(val, port_mmio + offset);
628 return 0;
629 }
630 return -EINVAL;
631 }
632
ahci_start_engine(struct ata_port * ap)633 void ahci_start_engine(struct ata_port *ap)
634 {
635 void __iomem *port_mmio = ahci_port_base(ap);
636 u32 tmp;
637
638 /* start DMA */
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp |= PORT_CMD_START;
641 writel(tmp, port_mmio + PORT_CMD);
642 readl(port_mmio + PORT_CMD); /* flush */
643 }
644 EXPORT_SYMBOL_GPL(ahci_start_engine);
645
ahci_stop_engine(struct ata_port * ap)646 int ahci_stop_engine(struct ata_port *ap)
647 {
648 void __iomem *port_mmio = ahci_port_base(ap);
649 struct ahci_host_priv *hpriv = ap->host->private_data;
650 u32 tmp;
651
652 /*
653 * On some controllers, stopping a port's DMA engine while the port
654 * is in ALPM state (partial or slumber) results in failures on
655 * subsequent DMA engine starts. For those controllers, put the
656 * port back in active state before stopping its DMA engine.
657 */
658 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
659 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
660 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
661 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
662 return -EIO;
663 }
664
665 tmp = readl(port_mmio + PORT_CMD);
666
667 /* check if the HBA is idle */
668 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
669 return 0;
670
671 /*
672 * Don't try to issue commands but return with ENODEV if the
673 * AHCI controller not available anymore (e.g. due to PCIe hot
674 * unplugging). Otherwise a 500ms delay for each port is added.
675 */
676 if (tmp == 0xffffffff) {
677 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
678 return -ENODEV;
679 }
680
681 /* setting HBA to idle */
682 tmp &= ~PORT_CMD_START;
683 writel(tmp, port_mmio + PORT_CMD);
684
685 /* wait for engine to stop. This could be as long as 500 msec */
686 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
687 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
688 if (tmp & PORT_CMD_LIST_ON)
689 return -EIO;
690
691 return 0;
692 }
693 EXPORT_SYMBOL_GPL(ahci_stop_engine);
694
ahci_start_fis_rx(struct ata_port * ap)695 void ahci_start_fis_rx(struct ata_port *ap)
696 {
697 void __iomem *port_mmio = ahci_port_base(ap);
698 struct ahci_host_priv *hpriv = ap->host->private_data;
699 struct ahci_port_priv *pp = ap->private_data;
700 u32 tmp;
701
702 /* set FIS registers */
703 if (hpriv->cap & HOST_CAP_64)
704 writel((pp->cmd_slot_dma >> 16) >> 16,
705 port_mmio + PORT_LST_ADDR_HI);
706 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
707
708 if (hpriv->cap & HOST_CAP_64)
709 writel((pp->rx_fis_dma >> 16) >> 16,
710 port_mmio + PORT_FIS_ADDR_HI);
711 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
712
713 /* enable FIS reception */
714 tmp = readl(port_mmio + PORT_CMD);
715 tmp |= PORT_CMD_FIS_RX;
716 writel(tmp, port_mmio + PORT_CMD);
717
718 /* flush */
719 readl(port_mmio + PORT_CMD);
720 }
721 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
722
ahci_stop_fis_rx(struct ata_port * ap)723 static int ahci_stop_fis_rx(struct ata_port *ap)
724 {
725 void __iomem *port_mmio = ahci_port_base(ap);
726 u32 tmp;
727
728 /* disable FIS reception */
729 tmp = readl(port_mmio + PORT_CMD);
730 tmp &= ~PORT_CMD_FIS_RX;
731 writel(tmp, port_mmio + PORT_CMD);
732
733 /* wait for completion, spec says 500ms, give it 1000 */
734 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
735 PORT_CMD_FIS_ON, 10, 1000);
736 if (tmp & PORT_CMD_FIS_ON)
737 return -EBUSY;
738
739 return 0;
740 }
741
ahci_power_up(struct ata_port * ap)742 static void ahci_power_up(struct ata_port *ap)
743 {
744 struct ahci_host_priv *hpriv = ap->host->private_data;
745 void __iomem *port_mmio = ahci_port_base(ap);
746 u32 cmd;
747
748 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
749
750 /* spin up device */
751 if (hpriv->cap & HOST_CAP_SSS) {
752 cmd |= PORT_CMD_SPIN_UP;
753 writel(cmd, port_mmio + PORT_CMD);
754 }
755
756 /* wake up link */
757 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
758 }
759
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)760 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
761 unsigned int hints)
762 {
763 struct ata_port *ap = link->ap;
764 struct ahci_host_priv *hpriv = ap->host->private_data;
765 struct ahci_port_priv *pp = ap->private_data;
766 void __iomem *port_mmio = ahci_port_base(ap);
767
768 if (policy != ATA_LPM_MAX_POWER) {
769 /* wakeup flag only applies to the max power policy */
770 hints &= ~ATA_LPM_WAKE_ONLY;
771
772 /*
773 * Disable interrupts on Phy Ready. This keeps us from
774 * getting woken up due to spurious phy ready
775 * interrupts.
776 */
777 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
778 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
779
780 sata_link_scr_lpm(link, policy, false);
781 }
782
783 if (hpriv->cap & HOST_CAP_ALPM) {
784 u32 cmd = readl(port_mmio + PORT_CMD);
785
786 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
787 if (!(hints & ATA_LPM_WAKE_ONLY))
788 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
789 cmd |= PORT_CMD_ICC_ACTIVE;
790
791 writel(cmd, port_mmio + PORT_CMD);
792 readl(port_mmio + PORT_CMD);
793
794 /* wait 10ms to be sure we've come out of LPM state */
795 ata_msleep(ap, 10);
796
797 if (hints & ATA_LPM_WAKE_ONLY)
798 return 0;
799 } else {
800 cmd |= PORT_CMD_ALPE;
801 if (policy == ATA_LPM_MIN_POWER)
802 cmd |= PORT_CMD_ASP;
803 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
804 cmd &= ~PORT_CMD_ASP;
805
806 /* write out new cmd value */
807 writel(cmd, port_mmio + PORT_CMD);
808 }
809 }
810
811 /* set aggressive device sleep */
812 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
813 (hpriv->cap2 & HOST_CAP2_SADM) &&
814 (link->device->flags & ATA_DFLAG_DEVSLP)) {
815 if (policy == ATA_LPM_MIN_POWER ||
816 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
817 ahci_set_aggressive_devslp(ap, true);
818 else
819 ahci_set_aggressive_devslp(ap, false);
820 }
821
822 if (policy == ATA_LPM_MAX_POWER) {
823 sata_link_scr_lpm(link, policy, false);
824
825 /* turn PHYRDY IRQ back on */
826 pp->intr_mask |= PORT_IRQ_PHYRDY;
827 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
828 }
829
830 return 0;
831 }
832
833 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)834 static void ahci_power_down(struct ata_port *ap)
835 {
836 struct ahci_host_priv *hpriv = ap->host->private_data;
837 void __iomem *port_mmio = ahci_port_base(ap);
838 u32 cmd, scontrol;
839
840 if (!(hpriv->cap & HOST_CAP_SSS))
841 return;
842
843 /* put device into listen mode, first set PxSCTL.DET to 0 */
844 scontrol = readl(port_mmio + PORT_SCR_CTL);
845 scontrol &= ~0xf;
846 writel(scontrol, port_mmio + PORT_SCR_CTL);
847
848 /* then set PxCMD.SUD to 0 */
849 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
850 cmd &= ~PORT_CMD_SPIN_UP;
851 writel(cmd, port_mmio + PORT_CMD);
852 }
853 #endif
854
ahci_start_port(struct ata_port * ap)855 static void ahci_start_port(struct ata_port *ap)
856 {
857 struct ahci_host_priv *hpriv = ap->host->private_data;
858 struct ahci_port_priv *pp = ap->private_data;
859 struct ata_link *link;
860 struct ahci_em_priv *emp;
861 ssize_t rc;
862 int i;
863
864 /* enable FIS reception */
865 ahci_start_fis_rx(ap);
866
867 /* enable DMA */
868 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
869 hpriv->start_engine(ap);
870
871 /* turn on LEDs */
872 if (ap->flags & ATA_FLAG_EM) {
873 ata_for_each_link(link, ap, EDGE) {
874 emp = &pp->em_priv[link->pmp];
875
876 /* EM Transmit bit maybe busy during init */
877 for (i = 0; i < EM_MAX_RETRY; i++) {
878 rc = ap->ops->transmit_led_message(ap,
879 emp->led_state,
880 4);
881 /*
882 * If busy, give a breather but do not
883 * release EH ownership by using msleep()
884 * instead of ata_msleep(). EM Transmit
885 * bit is busy for the whole host and
886 * releasing ownership will cause other
887 * ports to fail the same way.
888 */
889 if (rc == -EBUSY)
890 msleep(1);
891 else
892 break;
893 }
894 }
895 }
896
897 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
898 ata_for_each_link(link, ap, EDGE)
899 ahci_init_sw_activity(link);
900
901 }
902
ahci_deinit_port(struct ata_port * ap,const char ** emsg)903 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
904 {
905 int rc;
906 struct ahci_host_priv *hpriv = ap->host->private_data;
907
908 /* disable DMA */
909 rc = hpriv->stop_engine(ap);
910 if (rc) {
911 *emsg = "failed to stop engine";
912 return rc;
913 }
914
915 /* disable FIS reception */
916 rc = ahci_stop_fis_rx(ap);
917 if (rc) {
918 *emsg = "failed stop FIS RX";
919 return rc;
920 }
921
922 return 0;
923 }
924
ahci_reset_controller(struct ata_host * host)925 int ahci_reset_controller(struct ata_host *host)
926 {
927 struct ahci_host_priv *hpriv = host->private_data;
928 void __iomem *mmio = hpriv->mmio;
929 u32 tmp;
930
931 /* we must be in AHCI mode, before using anything
932 * AHCI-specific, such as HOST_RESET.
933 */
934 ahci_enable_ahci(mmio);
935
936 /* global controller reset */
937 if (!ahci_skip_host_reset) {
938 tmp = readl(mmio + HOST_CTL);
939 if ((tmp & HOST_RESET) == 0) {
940 writel(tmp | HOST_RESET, mmio + HOST_CTL);
941 readl(mmio + HOST_CTL); /* flush */
942 }
943
944 /*
945 * to perform host reset, OS should set HOST_RESET
946 * and poll until this bit is read to be "0".
947 * reset must complete within 1 second, or
948 * the hardware should be considered fried.
949 */
950 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
951 HOST_RESET, 10, 1000);
952
953 if (tmp & HOST_RESET) {
954 dev_err(host->dev, "controller reset failed (0x%x)\n",
955 tmp);
956 return -EIO;
957 }
958
959 /* turn on AHCI mode */
960 ahci_enable_ahci(mmio);
961
962 /* Some registers might be cleared on reset. Restore
963 * initial values.
964 */
965 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
966 ahci_restore_initial_config(host);
967 } else
968 dev_info(host->dev, "skipping global host reset\n");
969
970 return 0;
971 }
972 EXPORT_SYMBOL_GPL(ahci_reset_controller);
973
ahci_sw_activity(struct ata_link * link)974 static void ahci_sw_activity(struct ata_link *link)
975 {
976 struct ata_port *ap = link->ap;
977 struct ahci_port_priv *pp = ap->private_data;
978 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
979
980 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
981 return;
982
983 emp->activity++;
984 if (!timer_pending(&emp->timer))
985 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
986 }
987
ahci_sw_activity_blink(struct timer_list * t)988 static void ahci_sw_activity_blink(struct timer_list *t)
989 {
990 struct ahci_em_priv *emp = from_timer(emp, t, timer);
991 struct ata_link *link = emp->link;
992 struct ata_port *ap = link->ap;
993
994 unsigned long led_message = emp->led_state;
995 u32 activity_led_state;
996 unsigned long flags;
997
998 led_message &= EM_MSG_LED_VALUE;
999 led_message |= ap->port_no | (link->pmp << 8);
1000
1001 /* check to see if we've had activity. If so,
1002 * toggle state of LED and reset timer. If not,
1003 * turn LED to desired idle state.
1004 */
1005 spin_lock_irqsave(ap->lock, flags);
1006 if (emp->saved_activity != emp->activity) {
1007 emp->saved_activity = emp->activity;
1008 /* get the current LED state */
1009 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1010
1011 if (activity_led_state)
1012 activity_led_state = 0;
1013 else
1014 activity_led_state = 1;
1015
1016 /* clear old state */
1017 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1018
1019 /* toggle state */
1020 led_message |= (activity_led_state << 16);
1021 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1022 } else {
1023 /* switch to idle */
1024 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1025 if (emp->blink_policy == BLINK_OFF)
1026 led_message |= (1 << 16);
1027 }
1028 spin_unlock_irqrestore(ap->lock, flags);
1029 ap->ops->transmit_led_message(ap, led_message, 4);
1030 }
1031
ahci_init_sw_activity(struct ata_link * link)1032 static void ahci_init_sw_activity(struct ata_link *link)
1033 {
1034 struct ata_port *ap = link->ap;
1035 struct ahci_port_priv *pp = ap->private_data;
1036 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1037
1038 /* init activity stats, setup timer */
1039 emp->saved_activity = emp->activity = 0;
1040 emp->link = link;
1041 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1042
1043 /* check our blink policy and set flag for link if it's enabled */
1044 if (emp->blink_policy)
1045 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1046 }
1047
ahci_reset_em(struct ata_host * host)1048 int ahci_reset_em(struct ata_host *host)
1049 {
1050 struct ahci_host_priv *hpriv = host->private_data;
1051 void __iomem *mmio = hpriv->mmio;
1052 u32 em_ctl;
1053
1054 em_ctl = readl(mmio + HOST_EM_CTL);
1055 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1056 return -EINVAL;
1057
1058 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1059 return 0;
1060 }
1061 EXPORT_SYMBOL_GPL(ahci_reset_em);
1062
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)1063 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1064 ssize_t size)
1065 {
1066 struct ahci_host_priv *hpriv = ap->host->private_data;
1067 struct ahci_port_priv *pp = ap->private_data;
1068 void __iomem *mmio = hpriv->mmio;
1069 u32 em_ctl;
1070 u32 message[] = {0, 0};
1071 unsigned long flags;
1072 int pmp;
1073 struct ahci_em_priv *emp;
1074
1075 /* get the slot number from the message */
1076 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1077 if (pmp < EM_MAX_SLOTS)
1078 emp = &pp->em_priv[pmp];
1079 else
1080 return -EINVAL;
1081
1082 ahci_rpm_get_port(ap);
1083 spin_lock_irqsave(ap->lock, flags);
1084
1085 /*
1086 * if we are still busy transmitting a previous message,
1087 * do not allow
1088 */
1089 em_ctl = readl(mmio + HOST_EM_CTL);
1090 if (em_ctl & EM_CTL_TM) {
1091 spin_unlock_irqrestore(ap->lock, flags);
1092 ahci_rpm_put_port(ap);
1093 return -EBUSY;
1094 }
1095
1096 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1097 /*
1098 * create message header - this is all zero except for
1099 * the message size, which is 4 bytes.
1100 */
1101 message[0] |= (4 << 8);
1102
1103 /* ignore 0:4 of byte zero, fill in port info yourself */
1104 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1105
1106 /* write message to EM_LOC */
1107 writel(message[0], mmio + hpriv->em_loc);
1108 writel(message[1], mmio + hpriv->em_loc+4);
1109
1110 /*
1111 * tell hardware to transmit the message
1112 */
1113 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1114 }
1115
1116 /* save off new led state for port/slot */
1117 emp->led_state = state;
1118
1119 spin_unlock_irqrestore(ap->lock, flags);
1120 ahci_rpm_put_port(ap);
1121
1122 return size;
1123 }
1124
ahci_led_show(struct ata_port * ap,char * buf)1125 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1126 {
1127 struct ahci_port_priv *pp = ap->private_data;
1128 struct ata_link *link;
1129 struct ahci_em_priv *emp;
1130 int rc = 0;
1131
1132 ata_for_each_link(link, ap, EDGE) {
1133 emp = &pp->em_priv[link->pmp];
1134 rc += sprintf(buf, "%lx\n", emp->led_state);
1135 }
1136 return rc;
1137 }
1138
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1139 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1140 size_t size)
1141 {
1142 unsigned int state;
1143 int pmp;
1144 struct ahci_port_priv *pp = ap->private_data;
1145 struct ahci_em_priv *emp;
1146
1147 if (kstrtouint(buf, 0, &state) < 0)
1148 return -EINVAL;
1149
1150 /* get the slot number from the message */
1151 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1152 if (pmp < EM_MAX_SLOTS) {
1153 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1154 emp = &pp->em_priv[pmp];
1155 } else {
1156 return -EINVAL;
1157 }
1158
1159 /* mask off the activity bits if we are in sw_activity
1160 * mode, user should turn off sw_activity before setting
1161 * activity led through em_message
1162 */
1163 if (emp->blink_policy)
1164 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1165
1166 return ap->ops->transmit_led_message(ap, state, size);
1167 }
1168
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1169 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1170 {
1171 struct ata_link *link = dev->link;
1172 struct ata_port *ap = link->ap;
1173 struct ahci_port_priv *pp = ap->private_data;
1174 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1175 u32 port_led_state = emp->led_state;
1176
1177 /* save the desired Activity LED behavior */
1178 if (val == OFF) {
1179 /* clear LFLAG */
1180 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1181
1182 /* set the LED to OFF */
1183 port_led_state &= EM_MSG_LED_VALUE_OFF;
1184 port_led_state |= (ap->port_no | (link->pmp << 8));
1185 ap->ops->transmit_led_message(ap, port_led_state, 4);
1186 } else {
1187 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1188 if (val == BLINK_OFF) {
1189 /* set LED to ON for idle */
1190 port_led_state &= EM_MSG_LED_VALUE_OFF;
1191 port_led_state |= (ap->port_no | (link->pmp << 8));
1192 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1193 ap->ops->transmit_led_message(ap, port_led_state, 4);
1194 }
1195 }
1196 emp->blink_policy = val;
1197 return 0;
1198 }
1199
ahci_activity_show(struct ata_device * dev,char * buf)1200 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1201 {
1202 struct ata_link *link = dev->link;
1203 struct ata_port *ap = link->ap;
1204 struct ahci_port_priv *pp = ap->private_data;
1205 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1206
1207 /* display the saved value of activity behavior for this
1208 * disk.
1209 */
1210 return sprintf(buf, "%d\n", emp->blink_policy);
1211 }
1212
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1213 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1214 int port_no, void __iomem *mmio,
1215 void __iomem *port_mmio)
1216 {
1217 struct ahci_host_priv *hpriv = ap->host->private_data;
1218 const char *emsg = NULL;
1219 int rc;
1220 u32 tmp;
1221
1222 /* make sure port is not active */
1223 rc = ahci_deinit_port(ap, &emsg);
1224 if (rc)
1225 dev_warn(dev, "%s (%d)\n", emsg, rc);
1226
1227 /* clear SError */
1228 tmp = readl(port_mmio + PORT_SCR_ERR);
1229 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1230 writel(tmp, port_mmio + PORT_SCR_ERR);
1231
1232 /* clear port IRQ */
1233 tmp = readl(port_mmio + PORT_IRQ_STAT);
1234 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1235 if (tmp)
1236 writel(tmp, port_mmio + PORT_IRQ_STAT);
1237
1238 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1239
1240 /* mark esata ports */
1241 tmp = readl(port_mmio + PORT_CMD);
1242 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1243 ap->pflags |= ATA_PFLAG_EXTERNAL;
1244 }
1245
ahci_init_controller(struct ata_host * host)1246 void ahci_init_controller(struct ata_host *host)
1247 {
1248 struct ahci_host_priv *hpriv = host->private_data;
1249 void __iomem *mmio = hpriv->mmio;
1250 int i;
1251 void __iomem *port_mmio;
1252 u32 tmp;
1253
1254 for (i = 0; i < host->n_ports; i++) {
1255 struct ata_port *ap = host->ports[i];
1256
1257 port_mmio = ahci_port_base(ap);
1258 if (ata_port_is_dummy(ap))
1259 continue;
1260
1261 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1262 }
1263
1264 tmp = readl(mmio + HOST_CTL);
1265 VPRINTK("HOST_CTL 0x%x\n", tmp);
1266 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1267 tmp = readl(mmio + HOST_CTL);
1268 VPRINTK("HOST_CTL 0x%x\n", tmp);
1269 }
1270 EXPORT_SYMBOL_GPL(ahci_init_controller);
1271
ahci_dev_config(struct ata_device * dev)1272 static void ahci_dev_config(struct ata_device *dev)
1273 {
1274 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1275
1276 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1277 dev->max_sectors = 255;
1278 ata_dev_info(dev,
1279 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1280 }
1281 }
1282
ahci_dev_classify(struct ata_port * ap)1283 unsigned int ahci_dev_classify(struct ata_port *ap)
1284 {
1285 void __iomem *port_mmio = ahci_port_base(ap);
1286 struct ata_taskfile tf;
1287 u32 tmp;
1288
1289 tmp = readl(port_mmio + PORT_SIG);
1290 tf.lbah = (tmp >> 24) & 0xff;
1291 tf.lbam = (tmp >> 16) & 0xff;
1292 tf.lbal = (tmp >> 8) & 0xff;
1293 tf.nsect = (tmp) & 0xff;
1294
1295 return ata_dev_classify(&tf);
1296 }
1297 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1298
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1299 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1300 u32 opts)
1301 {
1302 dma_addr_t cmd_tbl_dma;
1303
1304 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1305
1306 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1307 pp->cmd_slot[tag].status = 0;
1308 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1309 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1310 }
1311 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1312
ahci_kick_engine(struct ata_port * ap)1313 int ahci_kick_engine(struct ata_port *ap)
1314 {
1315 void __iomem *port_mmio = ahci_port_base(ap);
1316 struct ahci_host_priv *hpriv = ap->host->private_data;
1317 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1318 u32 tmp;
1319 int busy, rc;
1320
1321 /* stop engine */
1322 rc = hpriv->stop_engine(ap);
1323 if (rc)
1324 goto out_restart;
1325
1326 /* need to do CLO?
1327 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1328 */
1329 busy = status & (ATA_BUSY | ATA_DRQ);
1330 if (!busy && !sata_pmp_attached(ap)) {
1331 rc = 0;
1332 goto out_restart;
1333 }
1334
1335 if (!(hpriv->cap & HOST_CAP_CLO)) {
1336 rc = -EOPNOTSUPP;
1337 goto out_restart;
1338 }
1339
1340 /* perform CLO */
1341 tmp = readl(port_mmio + PORT_CMD);
1342 tmp |= PORT_CMD_CLO;
1343 writel(tmp, port_mmio + PORT_CMD);
1344
1345 rc = 0;
1346 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1347 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1348 if (tmp & PORT_CMD_CLO)
1349 rc = -EIO;
1350
1351 /* restart engine */
1352 out_restart:
1353 hpriv->start_engine(ap);
1354 return rc;
1355 }
1356 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1357
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned long timeout_msec)1358 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1359 struct ata_taskfile *tf, int is_cmd, u16 flags,
1360 unsigned long timeout_msec)
1361 {
1362 const u32 cmd_fis_len = 5; /* five dwords */
1363 struct ahci_port_priv *pp = ap->private_data;
1364 void __iomem *port_mmio = ahci_port_base(ap);
1365 u8 *fis = pp->cmd_tbl;
1366 u32 tmp;
1367
1368 /* prep the command */
1369 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1370 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1371
1372 /* set port value for softreset of Port Multiplier */
1373 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1374 tmp = readl(port_mmio + PORT_FBS);
1375 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1376 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1377 writel(tmp, port_mmio + PORT_FBS);
1378 pp->fbs_last_dev = pmp;
1379 }
1380
1381 /* issue & wait */
1382 writel(1, port_mmio + PORT_CMD_ISSUE);
1383
1384 if (timeout_msec) {
1385 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1386 0x1, 0x1, 1, timeout_msec);
1387 if (tmp & 0x1) {
1388 ahci_kick_engine(ap);
1389 return -EBUSY;
1390 }
1391 } else
1392 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1393
1394 return 0;
1395 }
1396
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1397 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1398 int pmp, unsigned long deadline,
1399 int (*check_ready)(struct ata_link *link))
1400 {
1401 struct ata_port *ap = link->ap;
1402 struct ahci_host_priv *hpriv = ap->host->private_data;
1403 struct ahci_port_priv *pp = ap->private_data;
1404 const char *reason = NULL;
1405 unsigned long now, msecs;
1406 struct ata_taskfile tf;
1407 bool fbs_disabled = false;
1408 int rc;
1409
1410 DPRINTK("ENTER\n");
1411
1412 /* prepare for SRST (AHCI-1.1 10.4.1) */
1413 rc = ahci_kick_engine(ap);
1414 if (rc && rc != -EOPNOTSUPP)
1415 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1416
1417 /*
1418 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1419 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1420 * that is attached to port multiplier.
1421 */
1422 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1423 ahci_disable_fbs(ap);
1424 fbs_disabled = true;
1425 }
1426
1427 ata_tf_init(link->device, &tf);
1428
1429 /* issue the first H2D Register FIS */
1430 msecs = 0;
1431 now = jiffies;
1432 if (time_after(deadline, now))
1433 msecs = jiffies_to_msecs(deadline - now);
1434
1435 tf.ctl |= ATA_SRST;
1436 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1437 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1438 rc = -EIO;
1439 reason = "1st FIS failed";
1440 goto fail;
1441 }
1442
1443 /* spec says at least 5us, but be generous and sleep for 1ms */
1444 ata_msleep(ap, 1);
1445
1446 /* issue the second H2D Register FIS */
1447 tf.ctl &= ~ATA_SRST;
1448 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1449
1450 /* wait for link to become ready */
1451 rc = ata_wait_after_reset(link, deadline, check_ready);
1452 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1453 /*
1454 * Workaround for cases where link online status can't
1455 * be trusted. Treat device readiness timeout as link
1456 * offline.
1457 */
1458 ata_link_info(link, "device not ready, treating as offline\n");
1459 *class = ATA_DEV_NONE;
1460 } else if (rc) {
1461 /* link occupied, -ENODEV too is an error */
1462 reason = "device not ready";
1463 goto fail;
1464 } else
1465 *class = ahci_dev_classify(ap);
1466
1467 /* re-enable FBS if disabled before */
1468 if (fbs_disabled)
1469 ahci_enable_fbs(ap);
1470
1471 DPRINTK("EXIT, class=%u\n", *class);
1472 return 0;
1473
1474 fail:
1475 ata_link_err(link, "softreset failed (%s)\n", reason);
1476 return rc;
1477 }
1478
ahci_check_ready(struct ata_link * link)1479 int ahci_check_ready(struct ata_link *link)
1480 {
1481 void __iomem *port_mmio = ahci_port_base(link->ap);
1482 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1483
1484 return ata_check_ready(status);
1485 }
1486 EXPORT_SYMBOL_GPL(ahci_check_ready);
1487
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1488 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1489 unsigned long deadline)
1490 {
1491 int pmp = sata_srst_pmp(link);
1492
1493 DPRINTK("ENTER\n");
1494
1495 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1496 }
1497 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1498
ahci_bad_pmp_check_ready(struct ata_link * link)1499 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1500 {
1501 void __iomem *port_mmio = ahci_port_base(link->ap);
1502 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1503 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1504
1505 /*
1506 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1507 * which can save timeout delay.
1508 */
1509 if (irq_status & PORT_IRQ_BAD_PMP)
1510 return -EIO;
1511
1512 return ata_check_ready(status);
1513 }
1514
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1515 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1516 unsigned long deadline)
1517 {
1518 struct ata_port *ap = link->ap;
1519 void __iomem *port_mmio = ahci_port_base(ap);
1520 int pmp = sata_srst_pmp(link);
1521 int rc;
1522 u32 irq_sts;
1523
1524 DPRINTK("ENTER\n");
1525
1526 rc = ahci_do_softreset(link, class, pmp, deadline,
1527 ahci_bad_pmp_check_ready);
1528
1529 /*
1530 * Soft reset fails with IPMS set when PMP is enabled but
1531 * SATA HDD/ODD is connected to SATA port, do soft reset
1532 * again to port 0.
1533 */
1534 if (rc == -EIO) {
1535 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1536 if (irq_sts & PORT_IRQ_BAD_PMP) {
1537 ata_link_warn(link,
1538 "applying PMP SRST workaround "
1539 "and retrying\n");
1540 rc = ahci_do_softreset(link, class, 0, deadline,
1541 ahci_check_ready);
1542 }
1543 }
1544
1545 return rc;
1546 }
1547
ahci_do_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline,bool * online)1548 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1549 unsigned long deadline, bool *online)
1550 {
1551 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1552 struct ata_port *ap = link->ap;
1553 struct ahci_port_priv *pp = ap->private_data;
1554 struct ahci_host_priv *hpriv = ap->host->private_data;
1555 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1556 struct ata_taskfile tf;
1557 int rc;
1558
1559 DPRINTK("ENTER\n");
1560
1561 hpriv->stop_engine(ap);
1562
1563 /* clear D2H reception area to properly wait for D2H FIS */
1564 ata_tf_init(link->device, &tf);
1565 tf.command = ATA_BUSY;
1566 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1567
1568 rc = sata_link_hardreset(link, timing, deadline, online,
1569 ahci_check_ready);
1570
1571 hpriv->start_engine(ap);
1572
1573 if (*online)
1574 *class = ahci_dev_classify(ap);
1575
1576 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1577 return rc;
1578 }
1579 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1580
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1581 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1582 unsigned long deadline)
1583 {
1584 bool online;
1585
1586 return ahci_do_hardreset(link, class, deadline, &online);
1587 }
1588
ahci_postreset(struct ata_link * link,unsigned int * class)1589 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1590 {
1591 struct ata_port *ap = link->ap;
1592 void __iomem *port_mmio = ahci_port_base(ap);
1593 u32 new_tmp, tmp;
1594
1595 ata_std_postreset(link, class);
1596
1597 /* Make sure port's ATAPI bit is set appropriately */
1598 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1599 if (*class == ATA_DEV_ATAPI)
1600 new_tmp |= PORT_CMD_ATAPI;
1601 else
1602 new_tmp &= ~PORT_CMD_ATAPI;
1603 if (new_tmp != tmp) {
1604 writel(new_tmp, port_mmio + PORT_CMD);
1605 readl(port_mmio + PORT_CMD); /* flush */
1606 }
1607 }
1608
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1609 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1610 {
1611 struct scatterlist *sg;
1612 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1613 unsigned int si;
1614
1615 VPRINTK("ENTER\n");
1616
1617 /*
1618 * Next, the S/G list.
1619 */
1620 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1621 dma_addr_t addr = sg_dma_address(sg);
1622 u32 sg_len = sg_dma_len(sg);
1623
1624 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1625 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1626 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1627 }
1628
1629 return si;
1630 }
1631
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1632 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1633 {
1634 struct ata_port *ap = qc->ap;
1635 struct ahci_port_priv *pp = ap->private_data;
1636
1637 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1638 return ata_std_qc_defer(qc);
1639 else
1640 return sata_pmp_qc_defer_cmd_switch(qc);
1641 }
1642
ahci_qc_prep(struct ata_queued_cmd * qc)1643 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1644 {
1645 struct ata_port *ap = qc->ap;
1646 struct ahci_port_priv *pp = ap->private_data;
1647 int is_atapi = ata_is_atapi(qc->tf.protocol);
1648 void *cmd_tbl;
1649 u32 opts;
1650 const u32 cmd_fis_len = 5; /* five dwords */
1651 unsigned int n_elem;
1652
1653 /*
1654 * Fill in command table information. First, the header,
1655 * a SATA Register - Host to Device command FIS.
1656 */
1657 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1658
1659 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1660 if (is_atapi) {
1661 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1662 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1663 }
1664
1665 n_elem = 0;
1666 if (qc->flags & ATA_QCFLAG_DMAMAP)
1667 n_elem = ahci_fill_sg(qc, cmd_tbl);
1668
1669 /*
1670 * Fill in command slot information.
1671 */
1672 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1673 if (qc->tf.flags & ATA_TFLAG_WRITE)
1674 opts |= AHCI_CMD_WRITE;
1675 if (is_atapi)
1676 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1677
1678 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1679
1680 return AC_ERR_OK;
1681 }
1682
ahci_fbs_dec_intr(struct ata_port * ap)1683 static void ahci_fbs_dec_intr(struct ata_port *ap)
1684 {
1685 struct ahci_port_priv *pp = ap->private_data;
1686 void __iomem *port_mmio = ahci_port_base(ap);
1687 u32 fbs = readl(port_mmio + PORT_FBS);
1688 int retries = 3;
1689
1690 DPRINTK("ENTER\n");
1691 BUG_ON(!pp->fbs_enabled);
1692
1693 /* time to wait for DEC is not specified by AHCI spec,
1694 * add a retry loop for safety.
1695 */
1696 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1697 fbs = readl(port_mmio + PORT_FBS);
1698 while ((fbs & PORT_FBS_DEC) && retries--) {
1699 udelay(1);
1700 fbs = readl(port_mmio + PORT_FBS);
1701 }
1702
1703 if (fbs & PORT_FBS_DEC)
1704 dev_err(ap->host->dev, "failed to clear device error\n");
1705 }
1706
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1707 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1708 {
1709 struct ahci_host_priv *hpriv = ap->host->private_data;
1710 struct ahci_port_priv *pp = ap->private_data;
1711 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1712 struct ata_link *link = NULL;
1713 struct ata_queued_cmd *active_qc;
1714 struct ata_eh_info *active_ehi;
1715 bool fbs_need_dec = false;
1716 u32 serror;
1717
1718 /* determine active link with error */
1719 if (pp->fbs_enabled) {
1720 void __iomem *port_mmio = ahci_port_base(ap);
1721 u32 fbs = readl(port_mmio + PORT_FBS);
1722 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1723
1724 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1725 link = &ap->pmp_link[pmp];
1726 fbs_need_dec = true;
1727 }
1728
1729 } else
1730 ata_for_each_link(link, ap, EDGE)
1731 if (ata_link_active(link))
1732 break;
1733
1734 if (!link)
1735 link = &ap->link;
1736
1737 active_qc = ata_qc_from_tag(ap, link->active_tag);
1738 active_ehi = &link->eh_info;
1739
1740 /* record irq stat */
1741 ata_ehi_clear_desc(host_ehi);
1742 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1743
1744 /* AHCI needs SError cleared; otherwise, it might lock up */
1745 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1746 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1747 host_ehi->serror |= serror;
1748
1749 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1750 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1751 irq_stat &= ~PORT_IRQ_IF_ERR;
1752
1753 if (irq_stat & PORT_IRQ_TF_ERR) {
1754 /* If qc is active, charge it; otherwise, the active
1755 * link. There's no active qc on NCQ errors. It will
1756 * be determined by EH by reading log page 10h.
1757 */
1758 if (active_qc)
1759 active_qc->err_mask |= AC_ERR_DEV;
1760 else
1761 active_ehi->err_mask |= AC_ERR_DEV;
1762
1763 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1764 host_ehi->serror &= ~SERR_INTERNAL;
1765 }
1766
1767 if (irq_stat & PORT_IRQ_UNK_FIS) {
1768 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1769
1770 active_ehi->err_mask |= AC_ERR_HSM;
1771 active_ehi->action |= ATA_EH_RESET;
1772 ata_ehi_push_desc(active_ehi,
1773 "unknown FIS %08x %08x %08x %08x" ,
1774 unk[0], unk[1], unk[2], unk[3]);
1775 }
1776
1777 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1778 active_ehi->err_mask |= AC_ERR_HSM;
1779 active_ehi->action |= ATA_EH_RESET;
1780 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1781 }
1782
1783 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1784 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1785 host_ehi->action |= ATA_EH_RESET;
1786 ata_ehi_push_desc(host_ehi, "host bus error");
1787 }
1788
1789 if (irq_stat & PORT_IRQ_IF_ERR) {
1790 if (fbs_need_dec)
1791 active_ehi->err_mask |= AC_ERR_DEV;
1792 else {
1793 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1794 host_ehi->action |= ATA_EH_RESET;
1795 }
1796
1797 ata_ehi_push_desc(host_ehi, "interface fatal error");
1798 }
1799
1800 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1801 ata_ehi_hotplugged(host_ehi);
1802 ata_ehi_push_desc(host_ehi, "%s",
1803 irq_stat & PORT_IRQ_CONNECT ?
1804 "connection status changed" : "PHY RDY changed");
1805 }
1806
1807 /* okay, let's hand over to EH */
1808
1809 if (irq_stat & PORT_IRQ_FREEZE)
1810 ata_port_freeze(ap);
1811 else if (fbs_need_dec) {
1812 ata_link_abort(link);
1813 ahci_fbs_dec_intr(ap);
1814 } else
1815 ata_port_abort(ap);
1816 }
1817
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1818 static void ahci_handle_port_interrupt(struct ata_port *ap,
1819 void __iomem *port_mmio, u32 status)
1820 {
1821 struct ata_eh_info *ehi = &ap->link.eh_info;
1822 struct ahci_port_priv *pp = ap->private_data;
1823 struct ahci_host_priv *hpriv = ap->host->private_data;
1824 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1825 u32 qc_active = 0;
1826 int rc;
1827
1828 /* ignore BAD_PMP while resetting */
1829 if (unlikely(resetting))
1830 status &= ~PORT_IRQ_BAD_PMP;
1831
1832 if (sata_lpm_ignore_phy_events(&ap->link)) {
1833 status &= ~PORT_IRQ_PHYRDY;
1834 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1835 }
1836
1837 if (unlikely(status & PORT_IRQ_ERROR)) {
1838 ahci_error_intr(ap, status);
1839 return;
1840 }
1841
1842 if (status & PORT_IRQ_SDB_FIS) {
1843 /* If SNotification is available, leave notification
1844 * handling to sata_async_notification(). If not,
1845 * emulate it by snooping SDB FIS RX area.
1846 *
1847 * Snooping FIS RX area is probably cheaper than
1848 * poking SNotification but some constrollers which
1849 * implement SNotification, ICH9 for example, don't
1850 * store AN SDB FIS into receive area.
1851 */
1852 if (hpriv->cap & HOST_CAP_SNTF)
1853 sata_async_notification(ap);
1854 else {
1855 /* If the 'N' bit in word 0 of the FIS is set,
1856 * we just received asynchronous notification.
1857 * Tell libata about it.
1858 *
1859 * Lack of SNotification should not appear in
1860 * ahci 1.2, so the workaround is unnecessary
1861 * when FBS is enabled.
1862 */
1863 if (pp->fbs_enabled)
1864 WARN_ON_ONCE(1);
1865 else {
1866 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1867 u32 f0 = le32_to_cpu(f[0]);
1868 if (f0 & (1 << 15))
1869 sata_async_notification(ap);
1870 }
1871 }
1872 }
1873
1874 /* pp->active_link is not reliable once FBS is enabled, both
1875 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1876 * NCQ and non-NCQ commands may be in flight at the same time.
1877 */
1878 if (pp->fbs_enabled) {
1879 if (ap->qc_active) {
1880 qc_active = readl(port_mmio + PORT_SCR_ACT);
1881 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1882 }
1883 } else {
1884 /* pp->active_link is valid iff any command is in flight */
1885 if (ap->qc_active && pp->active_link->sactive)
1886 qc_active = readl(port_mmio + PORT_SCR_ACT);
1887 else
1888 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1889 }
1890
1891
1892 rc = ata_qc_complete_multiple(ap, qc_active);
1893
1894 /* while resetting, invalid completions are expected */
1895 if (unlikely(rc < 0 && !resetting)) {
1896 ehi->err_mask |= AC_ERR_HSM;
1897 ehi->action |= ATA_EH_RESET;
1898 ata_port_freeze(ap);
1899 }
1900 }
1901
ahci_port_intr(struct ata_port * ap)1902 static void ahci_port_intr(struct ata_port *ap)
1903 {
1904 void __iomem *port_mmio = ahci_port_base(ap);
1905 u32 status;
1906
1907 status = readl(port_mmio + PORT_IRQ_STAT);
1908 writel(status, port_mmio + PORT_IRQ_STAT);
1909
1910 ahci_handle_port_interrupt(ap, port_mmio, status);
1911 }
1912
ahci_multi_irqs_intr_hard(int irq,void * dev_instance)1913 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1914 {
1915 struct ata_port *ap = dev_instance;
1916 void __iomem *port_mmio = ahci_port_base(ap);
1917 u32 status;
1918
1919 VPRINTK("ENTER\n");
1920
1921 status = readl(port_mmio + PORT_IRQ_STAT);
1922 writel(status, port_mmio + PORT_IRQ_STAT);
1923
1924 spin_lock(ap->lock);
1925 ahci_handle_port_interrupt(ap, port_mmio, status);
1926 spin_unlock(ap->lock);
1927
1928 VPRINTK("EXIT\n");
1929
1930 return IRQ_HANDLED;
1931 }
1932
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1933 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1934 {
1935 unsigned int i, handled = 0;
1936
1937 for (i = 0; i < host->n_ports; i++) {
1938 struct ata_port *ap;
1939
1940 if (!(irq_masked & (1 << i)))
1941 continue;
1942
1943 ap = host->ports[i];
1944 if (ap) {
1945 ahci_port_intr(ap);
1946 VPRINTK("port %u\n", i);
1947 } else {
1948 VPRINTK("port %u (no irq)\n", i);
1949 if (ata_ratelimit())
1950 dev_warn(host->dev,
1951 "interrupt on disabled port %u\n", i);
1952 }
1953
1954 handled = 1;
1955 }
1956
1957 return handled;
1958 }
1959 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1960
ahci_single_level_irq_intr(int irq,void * dev_instance)1961 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1962 {
1963 struct ata_host *host = dev_instance;
1964 struct ahci_host_priv *hpriv;
1965 unsigned int rc = 0;
1966 void __iomem *mmio;
1967 u32 irq_stat, irq_masked;
1968
1969 VPRINTK("ENTER\n");
1970
1971 hpriv = host->private_data;
1972 mmio = hpriv->mmio;
1973
1974 /* sigh. 0xffffffff is a valid return from h/w */
1975 irq_stat = readl(mmio + HOST_IRQ_STAT);
1976 if (!irq_stat)
1977 return IRQ_NONE;
1978
1979 irq_masked = irq_stat & hpriv->port_map;
1980
1981 spin_lock(&host->lock);
1982
1983 rc = ahci_handle_port_intr(host, irq_masked);
1984
1985 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1986 * it should be cleared after all the port events are cleared;
1987 * otherwise, it will raise a spurious interrupt after each
1988 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1989 * information.
1990 *
1991 * Also, use the unmasked value to clear interrupt as spurious
1992 * pending event on a dummy port might cause screaming IRQ.
1993 */
1994 writel(irq_stat, mmio + HOST_IRQ_STAT);
1995
1996 spin_unlock(&host->lock);
1997
1998 VPRINTK("EXIT\n");
1999
2000 return IRQ_RETVAL(rc);
2001 }
2002
ahci_qc_issue(struct ata_queued_cmd * qc)2003 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2004 {
2005 struct ata_port *ap = qc->ap;
2006 void __iomem *port_mmio = ahci_port_base(ap);
2007 struct ahci_port_priv *pp = ap->private_data;
2008
2009 /* Keep track of the currently active link. It will be used
2010 * in completion path to determine whether NCQ phase is in
2011 * progress.
2012 */
2013 pp->active_link = qc->dev->link;
2014
2015 if (ata_is_ncq(qc->tf.protocol))
2016 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2017
2018 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2019 u32 fbs = readl(port_mmio + PORT_FBS);
2020 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2021 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2022 writel(fbs, port_mmio + PORT_FBS);
2023 pp->fbs_last_dev = qc->dev->link->pmp;
2024 }
2025
2026 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2027
2028 ahci_sw_activity(qc->dev->link);
2029
2030 return 0;
2031 }
2032 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2033
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)2034 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2035 {
2036 struct ahci_port_priv *pp = qc->ap->private_data;
2037 u8 *rx_fis = pp->rx_fis;
2038
2039 if (pp->fbs_enabled)
2040 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2041
2042 /*
2043 * After a successful execution of an ATA PIO data-in command,
2044 * the device doesn't send D2H Reg FIS to update the TF and
2045 * the host should take TF and E_Status from the preceding PIO
2046 * Setup FIS.
2047 */
2048 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2049 !(qc->flags & ATA_QCFLAG_FAILED)) {
2050 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2051 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2052 } else
2053 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2054
2055 return true;
2056 }
2057
ahci_freeze(struct ata_port * ap)2058 static void ahci_freeze(struct ata_port *ap)
2059 {
2060 void __iomem *port_mmio = ahci_port_base(ap);
2061
2062 /* turn IRQ off */
2063 writel(0, port_mmio + PORT_IRQ_MASK);
2064 }
2065
ahci_thaw(struct ata_port * ap)2066 static void ahci_thaw(struct ata_port *ap)
2067 {
2068 struct ahci_host_priv *hpriv = ap->host->private_data;
2069 void __iomem *mmio = hpriv->mmio;
2070 void __iomem *port_mmio = ahci_port_base(ap);
2071 u32 tmp;
2072 struct ahci_port_priv *pp = ap->private_data;
2073
2074 /* clear IRQ */
2075 tmp = readl(port_mmio + PORT_IRQ_STAT);
2076 writel(tmp, port_mmio + PORT_IRQ_STAT);
2077 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2078
2079 /* turn IRQ back on */
2080 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2081 }
2082
ahci_error_handler(struct ata_port * ap)2083 void ahci_error_handler(struct ata_port *ap)
2084 {
2085 struct ahci_host_priv *hpriv = ap->host->private_data;
2086
2087 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2088 /* restart engine */
2089 hpriv->stop_engine(ap);
2090 hpriv->start_engine(ap);
2091 }
2092
2093 sata_pmp_error_handler(ap);
2094
2095 if (!ata_dev_enabled(ap->link.device))
2096 hpriv->stop_engine(ap);
2097 }
2098 EXPORT_SYMBOL_GPL(ahci_error_handler);
2099
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2100 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2101 {
2102 struct ata_port *ap = qc->ap;
2103
2104 /* make DMA engine forget about the failed command */
2105 if (qc->flags & ATA_QCFLAG_FAILED)
2106 ahci_kick_engine(ap);
2107 }
2108
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2109 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2110 {
2111 struct ahci_host_priv *hpriv = ap->host->private_data;
2112 void __iomem *port_mmio = ahci_port_base(ap);
2113 struct ata_device *dev = ap->link.device;
2114 u32 devslp, dm, dito, mdat, deto, dito_conf;
2115 int rc;
2116 unsigned int err_mask;
2117
2118 devslp = readl(port_mmio + PORT_DEVSLP);
2119 if (!(devslp & PORT_DEVSLP_DSP)) {
2120 dev_info(ap->host->dev, "port does not support device sleep\n");
2121 return;
2122 }
2123
2124 /* disable device sleep */
2125 if (!sleep) {
2126 if (devslp & PORT_DEVSLP_ADSE) {
2127 writel(devslp & ~PORT_DEVSLP_ADSE,
2128 port_mmio + PORT_DEVSLP);
2129 err_mask = ata_dev_set_feature(dev,
2130 SETFEATURES_SATA_DISABLE,
2131 SATA_DEVSLP);
2132 if (err_mask && err_mask != AC_ERR_DEV)
2133 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2134 }
2135 return;
2136 }
2137
2138 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2139 dito = devslp_idle_timeout / (dm + 1);
2140 if (dito > 0x3ff)
2141 dito = 0x3ff;
2142
2143 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2144
2145 /* device sleep was already enabled and same dito */
2146 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2147 return;
2148
2149 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2150 rc = hpriv->stop_engine(ap);
2151 if (rc)
2152 return;
2153
2154 /* Use the nominal value 10 ms if the read MDAT is zero,
2155 * the nominal value of DETO is 20 ms.
2156 */
2157 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2158 ATA_LOG_DEVSLP_VALID_MASK) {
2159 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2160 ATA_LOG_DEVSLP_MDAT_MASK;
2161 if (!mdat)
2162 mdat = 10;
2163 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2164 if (!deto)
2165 deto = 20;
2166 } else {
2167 mdat = 10;
2168 deto = 20;
2169 }
2170
2171 /* Make dito, mdat, deto bits to 0s */
2172 devslp &= ~GENMASK_ULL(24, 2);
2173 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2174 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2175 (deto << PORT_DEVSLP_DETO_OFFSET) |
2176 PORT_DEVSLP_ADSE);
2177 writel(devslp, port_mmio + PORT_DEVSLP);
2178
2179 hpriv->start_engine(ap);
2180
2181 /* enable device sleep feature for the drive */
2182 err_mask = ata_dev_set_feature(dev,
2183 SETFEATURES_SATA_ENABLE,
2184 SATA_DEVSLP);
2185 if (err_mask && err_mask != AC_ERR_DEV)
2186 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2187 }
2188
ahci_enable_fbs(struct ata_port * ap)2189 static void ahci_enable_fbs(struct ata_port *ap)
2190 {
2191 struct ahci_host_priv *hpriv = ap->host->private_data;
2192 struct ahci_port_priv *pp = ap->private_data;
2193 void __iomem *port_mmio = ahci_port_base(ap);
2194 u32 fbs;
2195 int rc;
2196
2197 if (!pp->fbs_supported)
2198 return;
2199
2200 fbs = readl(port_mmio + PORT_FBS);
2201 if (fbs & PORT_FBS_EN) {
2202 pp->fbs_enabled = true;
2203 pp->fbs_last_dev = -1; /* initialization */
2204 return;
2205 }
2206
2207 rc = hpriv->stop_engine(ap);
2208 if (rc)
2209 return;
2210
2211 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2212 fbs = readl(port_mmio + PORT_FBS);
2213 if (fbs & PORT_FBS_EN) {
2214 dev_info(ap->host->dev, "FBS is enabled\n");
2215 pp->fbs_enabled = true;
2216 pp->fbs_last_dev = -1; /* initialization */
2217 } else
2218 dev_err(ap->host->dev, "Failed to enable FBS\n");
2219
2220 hpriv->start_engine(ap);
2221 }
2222
ahci_disable_fbs(struct ata_port * ap)2223 static void ahci_disable_fbs(struct ata_port *ap)
2224 {
2225 struct ahci_host_priv *hpriv = ap->host->private_data;
2226 struct ahci_port_priv *pp = ap->private_data;
2227 void __iomem *port_mmio = ahci_port_base(ap);
2228 u32 fbs;
2229 int rc;
2230
2231 if (!pp->fbs_supported)
2232 return;
2233
2234 fbs = readl(port_mmio + PORT_FBS);
2235 if ((fbs & PORT_FBS_EN) == 0) {
2236 pp->fbs_enabled = false;
2237 return;
2238 }
2239
2240 rc = hpriv->stop_engine(ap);
2241 if (rc)
2242 return;
2243
2244 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2245 fbs = readl(port_mmio + PORT_FBS);
2246 if (fbs & PORT_FBS_EN)
2247 dev_err(ap->host->dev, "Failed to disable FBS\n");
2248 else {
2249 dev_info(ap->host->dev, "FBS is disabled\n");
2250 pp->fbs_enabled = false;
2251 }
2252
2253 hpriv->start_engine(ap);
2254 }
2255
ahci_pmp_attach(struct ata_port * ap)2256 static void ahci_pmp_attach(struct ata_port *ap)
2257 {
2258 void __iomem *port_mmio = ahci_port_base(ap);
2259 struct ahci_port_priv *pp = ap->private_data;
2260 u32 cmd;
2261
2262 cmd = readl(port_mmio + PORT_CMD);
2263 cmd |= PORT_CMD_PMP;
2264 writel(cmd, port_mmio + PORT_CMD);
2265
2266 ahci_enable_fbs(ap);
2267
2268 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2269
2270 /*
2271 * We must not change the port interrupt mask register if the
2272 * port is marked frozen, the value in pp->intr_mask will be
2273 * restored later when the port is thawed.
2274 *
2275 * Note that during initialization, the port is marked as
2276 * frozen since the irq handler is not yet registered.
2277 */
2278 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2279 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2280 }
2281
ahci_pmp_detach(struct ata_port * ap)2282 static void ahci_pmp_detach(struct ata_port *ap)
2283 {
2284 void __iomem *port_mmio = ahci_port_base(ap);
2285 struct ahci_port_priv *pp = ap->private_data;
2286 u32 cmd;
2287
2288 ahci_disable_fbs(ap);
2289
2290 cmd = readl(port_mmio + PORT_CMD);
2291 cmd &= ~PORT_CMD_PMP;
2292 writel(cmd, port_mmio + PORT_CMD);
2293
2294 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2295
2296 /* see comment above in ahci_pmp_attach() */
2297 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2298 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2299 }
2300
ahci_port_resume(struct ata_port * ap)2301 int ahci_port_resume(struct ata_port *ap)
2302 {
2303 ahci_rpm_get_port(ap);
2304
2305 ahci_power_up(ap);
2306 ahci_start_port(ap);
2307
2308 if (sata_pmp_attached(ap))
2309 ahci_pmp_attach(ap);
2310 else
2311 ahci_pmp_detach(ap);
2312
2313 return 0;
2314 }
2315 EXPORT_SYMBOL_GPL(ahci_port_resume);
2316
2317 #ifdef CONFIG_PM
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2318 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2319 {
2320 const char *emsg = NULL;
2321 int rc;
2322
2323 rc = ahci_deinit_port(ap, &emsg);
2324 if (rc == 0)
2325 ahci_power_down(ap);
2326 else {
2327 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2328 ata_port_freeze(ap);
2329 }
2330
2331 ahci_rpm_put_port(ap);
2332 return rc;
2333 }
2334 #endif
2335
ahci_port_start(struct ata_port * ap)2336 static int ahci_port_start(struct ata_port *ap)
2337 {
2338 struct ahci_host_priv *hpriv = ap->host->private_data;
2339 struct device *dev = ap->host->dev;
2340 struct ahci_port_priv *pp;
2341 void *mem;
2342 dma_addr_t mem_dma;
2343 size_t dma_sz, rx_fis_sz;
2344
2345 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2346 if (!pp)
2347 return -ENOMEM;
2348
2349 if (ap->host->n_ports > 1) {
2350 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2351 if (!pp->irq_desc) {
2352 devm_kfree(dev, pp);
2353 return -ENOMEM;
2354 }
2355 snprintf(pp->irq_desc, 8,
2356 "%s%d", dev_driver_string(dev), ap->port_no);
2357 }
2358
2359 /* check FBS capability */
2360 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2361 void __iomem *port_mmio = ahci_port_base(ap);
2362 u32 cmd = readl(port_mmio + PORT_CMD);
2363 if (cmd & PORT_CMD_FBSCP)
2364 pp->fbs_supported = true;
2365 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2366 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2367 ap->port_no);
2368 pp->fbs_supported = true;
2369 } else
2370 dev_warn(dev, "port %d is not capable of FBS\n",
2371 ap->port_no);
2372 }
2373
2374 if (pp->fbs_supported) {
2375 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2376 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2377 } else {
2378 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2379 rx_fis_sz = AHCI_RX_FIS_SZ;
2380 }
2381
2382 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2383 if (!mem)
2384 return -ENOMEM;
2385 memset(mem, 0, dma_sz);
2386
2387 /*
2388 * First item in chunk of DMA memory: 32-slot command table,
2389 * 32 bytes each in size
2390 */
2391 pp->cmd_slot = mem;
2392 pp->cmd_slot_dma = mem_dma;
2393
2394 mem += AHCI_CMD_SLOT_SZ;
2395 mem_dma += AHCI_CMD_SLOT_SZ;
2396
2397 /*
2398 * Second item: Received-FIS area
2399 */
2400 pp->rx_fis = mem;
2401 pp->rx_fis_dma = mem_dma;
2402
2403 mem += rx_fis_sz;
2404 mem_dma += rx_fis_sz;
2405
2406 /*
2407 * Third item: data area for storing a single command
2408 * and its scatter-gather table
2409 */
2410 pp->cmd_tbl = mem;
2411 pp->cmd_tbl_dma = mem_dma;
2412
2413 /*
2414 * Save off initial list of interrupts to be enabled.
2415 * This could be changed later
2416 */
2417 pp->intr_mask = DEF_PORT_IRQ;
2418
2419 /*
2420 * Switch to per-port locking in case each port has its own MSI vector.
2421 */
2422 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2423 spin_lock_init(&pp->lock);
2424 ap->lock = &pp->lock;
2425 }
2426
2427 ap->private_data = pp;
2428
2429 /* engage engines, captain */
2430 return ahci_port_resume(ap);
2431 }
2432
ahci_port_stop(struct ata_port * ap)2433 static void ahci_port_stop(struct ata_port *ap)
2434 {
2435 const char *emsg = NULL;
2436 struct ahci_host_priv *hpriv = ap->host->private_data;
2437 void __iomem *host_mmio = hpriv->mmio;
2438 int rc;
2439
2440 /* de-initialize port */
2441 rc = ahci_deinit_port(ap, &emsg);
2442 if (rc)
2443 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2444
2445 /*
2446 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2447 * re-enabling INTx.
2448 */
2449 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2450
2451 ahci_rpm_put_port(ap);
2452 }
2453
ahci_print_info(struct ata_host * host,const char * scc_s)2454 void ahci_print_info(struct ata_host *host, const char *scc_s)
2455 {
2456 struct ahci_host_priv *hpriv = host->private_data;
2457 u32 vers, cap, cap2, impl, speed;
2458 const char *speed_s;
2459
2460 vers = hpriv->version;
2461 cap = hpriv->cap;
2462 cap2 = hpriv->cap2;
2463 impl = hpriv->port_map;
2464
2465 speed = (cap >> 20) & 0xf;
2466 if (speed == 1)
2467 speed_s = "1.5";
2468 else if (speed == 2)
2469 speed_s = "3";
2470 else if (speed == 3)
2471 speed_s = "6";
2472 else
2473 speed_s = "?";
2474
2475 dev_info(host->dev,
2476 "AHCI %02x%02x.%02x%02x "
2477 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2478 ,
2479
2480 (vers >> 24) & 0xff,
2481 (vers >> 16) & 0xff,
2482 (vers >> 8) & 0xff,
2483 vers & 0xff,
2484
2485 ((cap >> 8) & 0x1f) + 1,
2486 (cap & 0x1f) + 1,
2487 speed_s,
2488 impl,
2489 scc_s);
2490
2491 dev_info(host->dev,
2492 "flags: "
2493 "%s%s%s%s%s%s%s"
2494 "%s%s%s%s%s%s%s"
2495 "%s%s%s%s%s%s%s"
2496 "%s%s\n"
2497 ,
2498
2499 cap & HOST_CAP_64 ? "64bit " : "",
2500 cap & HOST_CAP_NCQ ? "ncq " : "",
2501 cap & HOST_CAP_SNTF ? "sntf " : "",
2502 cap & HOST_CAP_MPS ? "ilck " : "",
2503 cap & HOST_CAP_SSS ? "stag " : "",
2504 cap & HOST_CAP_ALPM ? "pm " : "",
2505 cap & HOST_CAP_LED ? "led " : "",
2506 cap & HOST_CAP_CLO ? "clo " : "",
2507 cap & HOST_CAP_ONLY ? "only " : "",
2508 cap & HOST_CAP_PMP ? "pmp " : "",
2509 cap & HOST_CAP_FBS ? "fbs " : "",
2510 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2511 cap & HOST_CAP_SSC ? "slum " : "",
2512 cap & HOST_CAP_PART ? "part " : "",
2513 cap & HOST_CAP_CCC ? "ccc " : "",
2514 cap & HOST_CAP_EMS ? "ems " : "",
2515 cap & HOST_CAP_SXS ? "sxs " : "",
2516 cap2 & HOST_CAP2_DESO ? "deso " : "",
2517 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2518 cap2 & HOST_CAP2_SDS ? "sds " : "",
2519 cap2 & HOST_CAP2_APST ? "apst " : "",
2520 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2521 cap2 & HOST_CAP2_BOH ? "boh " : ""
2522 );
2523 }
2524 EXPORT_SYMBOL_GPL(ahci_print_info);
2525
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2526 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2527 struct ata_port_info *pi)
2528 {
2529 u8 messages;
2530 void __iomem *mmio = hpriv->mmio;
2531 u32 em_loc = readl(mmio + HOST_EM_LOC);
2532 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2533
2534 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2535 return;
2536
2537 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2538
2539 if (messages) {
2540 /* store em_loc */
2541 hpriv->em_loc = ((em_loc >> 16) * 4);
2542 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2543 hpriv->em_msg_type = messages;
2544 pi->flags |= ATA_FLAG_EM;
2545 if (!(em_ctl & EM_CTL_ALHD))
2546 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2547 }
2548 }
2549 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2550
ahci_host_activate_multi_irqs(struct ata_host * host,struct scsi_host_template * sht)2551 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2552 struct scsi_host_template *sht)
2553 {
2554 struct ahci_host_priv *hpriv = host->private_data;
2555 int i, rc;
2556
2557 rc = ata_host_start(host);
2558 if (rc)
2559 return rc;
2560 /*
2561 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2562 * allocated. That is one MSI per port, starting from @irq.
2563 */
2564 for (i = 0; i < host->n_ports; i++) {
2565 struct ahci_port_priv *pp = host->ports[i]->private_data;
2566 int irq = hpriv->get_irq_vector(host, i);
2567
2568 /* Do not receive interrupts sent by dummy ports */
2569 if (!pp) {
2570 disable_irq(irq);
2571 continue;
2572 }
2573
2574 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2575 0, pp->irq_desc, host->ports[i]);
2576
2577 if (rc)
2578 return rc;
2579 ata_port_desc(host->ports[i], "irq %d", irq);
2580 }
2581
2582 return ata_host_register(host, sht);
2583 }
2584
2585 /**
2586 * ahci_host_activate - start AHCI host, request IRQs and register it
2587 * @host: target ATA host
2588 * @sht: scsi_host_template to use when registering the host
2589 *
2590 * LOCKING:
2591 * Inherited from calling layer (may sleep).
2592 *
2593 * RETURNS:
2594 * 0 on success, -errno otherwise.
2595 */
ahci_host_activate(struct ata_host * host,struct scsi_host_template * sht)2596 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2597 {
2598 struct ahci_host_priv *hpriv = host->private_data;
2599 int irq = hpriv->irq;
2600 int rc;
2601
2602 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2603 if (hpriv->irq_handler)
2604 dev_warn(host->dev,
2605 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2606 if (!hpriv->get_irq_vector) {
2607 dev_err(host->dev,
2608 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2609 return -EIO;
2610 }
2611
2612 rc = ahci_host_activate_multi_irqs(host, sht);
2613 } else {
2614 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2615 IRQF_SHARED, sht);
2616 }
2617
2618
2619 return rc;
2620 }
2621 EXPORT_SYMBOL_GPL(ahci_host_activate);
2622
2623 MODULE_AUTHOR("Jeff Garzik");
2624 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2625 MODULE_LICENSE("GPL");
2626