1 /*
2 * Generic PXA PATA driver
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/blkdev.h>
24 #include <linux/ata.h>
25 #include <linux/libata.h>
26 #include <linux/platform_device.h>
27 #include <linux/dmaengine.h>
28 #include <linux/gpio.h>
29 #include <linux/slab.h>
30 #include <linux/completion.h>
31
32 #include <scsi/scsi_host.h>
33
34 #include <linux/platform_data/ata-pxa.h>
35
36 #define DRV_NAME "pata_pxa"
37 #define DRV_VERSION "0.1"
38
39 struct pata_pxa_data {
40 struct dma_chan *dma_chan;
41 dma_cookie_t dma_cookie;
42 struct completion dma_done;
43 };
44
45 /*
46 * DMA interrupt handler.
47 */
pxa_ata_dma_irq(void * d)48 static void pxa_ata_dma_irq(void *d)
49 {
50 struct pata_pxa_data *pd = d;
51 enum dma_status status;
52
53 status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
54 if (status == DMA_ERROR || status == DMA_COMPLETE)
55 complete(&pd->dma_done);
56 }
57
58 /*
59 * Prepare taskfile for submission.
60 */
pxa_qc_prep(struct ata_queued_cmd * qc)61 static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
62 {
63 struct pata_pxa_data *pd = qc->ap->private_data;
64 struct dma_async_tx_descriptor *tx;
65 enum dma_transfer_direction dir;
66
67 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
68 return AC_ERR_OK;
69
70 dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
71 tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
72 DMA_PREP_INTERRUPT);
73 if (!tx) {
74 ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
75 return AC_ERR_OK;
76 }
77 tx->callback = pxa_ata_dma_irq;
78 tx->callback_param = pd;
79 pd->dma_cookie = dmaengine_submit(tx);
80
81 return AC_ERR_OK;
82 }
83
84 /*
85 * Configure the DMA controller, load the DMA descriptors, but don't start the
86 * DMA controller yet. Only issue the ATA command.
87 */
pxa_bmdma_setup(struct ata_queued_cmd * qc)88 static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
89 {
90 qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
91 }
92
93 /*
94 * Execute the DMA transfer.
95 */
pxa_bmdma_start(struct ata_queued_cmd * qc)96 static void pxa_bmdma_start(struct ata_queued_cmd *qc)
97 {
98 struct pata_pxa_data *pd = qc->ap->private_data;
99 init_completion(&pd->dma_done);
100 dma_async_issue_pending(pd->dma_chan);
101 }
102
103 /*
104 * Wait until the DMA transfer completes, then stop the DMA controller.
105 */
pxa_bmdma_stop(struct ata_queued_cmd * qc)106 static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
107 {
108 struct pata_pxa_data *pd = qc->ap->private_data;
109 enum dma_status status;
110
111 status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
112 if (status != DMA_ERROR && status != DMA_COMPLETE &&
113 wait_for_completion_timeout(&pd->dma_done, HZ))
114 ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
115
116 dmaengine_terminate_all(pd->dma_chan);
117 }
118
119 /*
120 * Read DMA status. The bmdma_stop() will take care of properly finishing the
121 * DMA transfer so we always have DMA-complete interrupt here.
122 */
pxa_bmdma_status(struct ata_port * ap)123 static unsigned char pxa_bmdma_status(struct ata_port *ap)
124 {
125 struct pata_pxa_data *pd = ap->private_data;
126 unsigned char ret = ATA_DMA_INTR;
127 struct dma_tx_state state;
128 enum dma_status status;
129
130 status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
131 if (status != DMA_COMPLETE)
132 ret |= ATA_DMA_ERR;
133
134 return ret;
135 }
136
137 /*
138 * No IRQ register present so we do nothing.
139 */
pxa_irq_clear(struct ata_port * ap)140 static void pxa_irq_clear(struct ata_port *ap)
141 {
142 }
143
144 /*
145 * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
146 * unclear why ATAPI has DMA issues.
147 */
pxa_check_atapi_dma(struct ata_queued_cmd * qc)148 static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
149 {
150 return -EOPNOTSUPP;
151 }
152
153 static struct scsi_host_template pxa_ata_sht = {
154 ATA_BMDMA_SHT(DRV_NAME),
155 };
156
157 static struct ata_port_operations pxa_ata_port_ops = {
158 .inherits = &ata_bmdma_port_ops,
159 .cable_detect = ata_cable_40wire,
160
161 .bmdma_setup = pxa_bmdma_setup,
162 .bmdma_start = pxa_bmdma_start,
163 .bmdma_stop = pxa_bmdma_stop,
164 .bmdma_status = pxa_bmdma_status,
165
166 .check_atapi_dma = pxa_check_atapi_dma,
167
168 .sff_irq_clear = pxa_irq_clear,
169
170 .qc_prep = pxa_qc_prep,
171 };
172
pxa_ata_probe(struct platform_device * pdev)173 static int pxa_ata_probe(struct platform_device *pdev)
174 {
175 struct ata_host *host;
176 struct ata_port *ap;
177 struct pata_pxa_data *data;
178 struct resource *cmd_res;
179 struct resource *ctl_res;
180 struct resource *dma_res;
181 struct resource *irq_res;
182 struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
183 struct dma_slave_config config;
184 int ret = 0;
185
186 /*
187 * Resource validation, three resources are needed:
188 * - CMD port base address
189 * - CTL port base address
190 * - DMA port base address
191 * - IRQ pin
192 */
193 if (pdev->num_resources != 4) {
194 dev_err(&pdev->dev, "invalid number of resources\n");
195 return -EINVAL;
196 }
197
198 /*
199 * CMD port base address
200 */
201 cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 if (unlikely(cmd_res == NULL))
203 return -EINVAL;
204
205 /*
206 * CTL port base address
207 */
208 ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
209 if (unlikely(ctl_res == NULL))
210 return -EINVAL;
211
212 /*
213 * DMA port base address
214 */
215 dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
216 if (unlikely(dma_res == NULL))
217 return -EINVAL;
218
219 /*
220 * IRQ pin
221 */
222 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
223 if (unlikely(irq_res == NULL))
224 return -EINVAL;
225
226 /*
227 * Allocate the host
228 */
229 host = ata_host_alloc(&pdev->dev, 1);
230 if (!host)
231 return -ENOMEM;
232
233 ap = host->ports[0];
234 ap->ops = &pxa_ata_port_ops;
235 ap->pio_mask = ATA_PIO4;
236 ap->mwdma_mask = ATA_MWDMA2;
237
238 ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
239 resource_size(cmd_res));
240 ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
241 resource_size(ctl_res));
242 ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
243 resource_size(dma_res));
244
245 /*
246 * Adjust register offsets
247 */
248 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
249 ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
250 (ATA_REG_DATA << pdata->reg_shift);
251 ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
252 (ATA_REG_ERR << pdata->reg_shift);
253 ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
254 (ATA_REG_FEATURE << pdata->reg_shift);
255 ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
256 (ATA_REG_NSECT << pdata->reg_shift);
257 ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
258 (ATA_REG_LBAL << pdata->reg_shift);
259 ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
260 (ATA_REG_LBAM << pdata->reg_shift);
261 ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
262 (ATA_REG_LBAH << pdata->reg_shift);
263 ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
264 (ATA_REG_DEVICE << pdata->reg_shift);
265 ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
266 (ATA_REG_STATUS << pdata->reg_shift);
267 ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
268 (ATA_REG_CMD << pdata->reg_shift);
269
270 /*
271 * Allocate and load driver's internal data structure
272 */
273 data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
274 GFP_KERNEL);
275 if (!data)
276 return -ENOMEM;
277
278 ap->private_data = data;
279
280 memset(&config, 0, sizeof(config));
281 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
282 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
283 config.src_addr = dma_res->start;
284 config.dst_addr = dma_res->start;
285 config.src_maxburst = 32;
286 config.dst_maxburst = 32;
287
288 /*
289 * Request the DMA channel
290 */
291 data->dma_chan =
292 dma_request_slave_channel(&pdev->dev, "data");
293 if (!data->dma_chan)
294 return -EBUSY;
295 ret = dmaengine_slave_config(data->dma_chan, &config);
296 if (ret < 0) {
297 dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
298 return ret;
299 }
300
301 /*
302 * Activate the ATA host
303 */
304 ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
305 pdata->irq_flags, &pxa_ata_sht);
306 if (ret)
307 dma_release_channel(data->dma_chan);
308
309 return ret;
310 }
311
pxa_ata_remove(struct platform_device * pdev)312 static int pxa_ata_remove(struct platform_device *pdev)
313 {
314 struct ata_host *host = platform_get_drvdata(pdev);
315 struct pata_pxa_data *data = host->ports[0]->private_data;
316
317 dma_release_channel(data->dma_chan);
318
319 ata_host_detach(host);
320
321 return 0;
322 }
323
324 static struct platform_driver pxa_ata_driver = {
325 .probe = pxa_ata_probe,
326 .remove = pxa_ata_remove,
327 .driver = {
328 .name = DRV_NAME,
329 },
330 };
331
332 module_platform_driver(pxa_ata_driver);
333
334 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
335 MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
336 MODULE_LICENSE("GPL");
337 MODULE_VERSION(DRV_VERSION);
338 MODULE_ALIAS("platform:" DRV_NAME);
339