1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30
31 static unsigned int intr_coalescing_count;
32 module_param(intr_coalescing_count, int, S_IRUGO);
33 MODULE_PARM_DESC(intr_coalescing_count,
34 "INT coalescing count threshold (1..31)");
35
36 static unsigned int intr_coalescing_ticks;
37 module_param(intr_coalescing_ticks, int, S_IRUGO);
38 MODULE_PARM_DESC(intr_coalescing_ticks,
39 "INT coalescing timer threshold in AHB ticks");
40 /* Controller information */
41 enum {
42 SATA_FSL_QUEUE_DEPTH = 16,
43 SATA_FSL_MAX_PRD = 63,
44 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
45 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
46
47 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
48 ATA_FLAG_PMP | ATA_FLAG_NCQ |
49 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
50
51 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
52 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
53 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
54
55 /*
56 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
57 * chained indirect PRDEs up to a max count of 63.
58 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
59 * be setup as an indirect descriptor, pointing to it's next
60 * (contiguous) PRDE. Though chained indirect PRDE arrays are
61 * supported,it will be more efficient to use a direct PRDT and
62 * a single chain/link to indirect PRDE array/PRDT.
63 */
64
65 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
66 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
67 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
68 SATA_FSL_CMD_DESC_RSRVD = 16,
69
70 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
71 SATA_FSL_CMD_DESC_SFIS_SZ +
72 SATA_FSL_CMD_DESC_ACMD_SZ +
73 SATA_FSL_CMD_DESC_RSRVD +
74 SATA_FSL_MAX_PRD * 16),
75
76 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
77 (SATA_FSL_CMD_DESC_CFIS_SZ +
78 SATA_FSL_CMD_DESC_SFIS_SZ +
79 SATA_FSL_CMD_DESC_ACMD_SZ +
80 SATA_FSL_CMD_DESC_RSRVD),
81
82 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
83 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
84 SATA_FSL_CMD_DESC_AR_SZ),
85
86 /*
87 * MPC8315 has two SATA controllers, SATA1 & SATA2
88 * (one port per controller)
89 * MPC837x has 2/4 controllers, one port per controller
90 */
91
92 SATA_FSL_MAX_PORTS = 1,
93
94 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
95 };
96
97 /*
98 * Interrupt Coalescing Control Register bitdefs */
99 enum {
100 ICC_MIN_INT_COUNT_THRESHOLD = 1,
101 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
102 ICC_MIN_INT_TICKS_THRESHOLD = 0,
103 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
104 ICC_SAFE_INT_TICKS = 1,
105 };
106
107 /*
108 * Host Controller command register set - per port
109 */
110 enum {
111 CQ = 0,
112 CA = 8,
113 CC = 0x10,
114 CE = 0x18,
115 DE = 0x20,
116 CHBA = 0x24,
117 HSTATUS = 0x28,
118 HCONTROL = 0x2C,
119 CQPMP = 0x30,
120 SIGNATURE = 0x34,
121 ICC = 0x38,
122
123 /*
124 * Host Status Register (HStatus) bitdefs
125 */
126 ONLINE = (1 << 31),
127 GOING_OFFLINE = (1 << 30),
128 BIST_ERR = (1 << 29),
129 CLEAR_ERROR = (1 << 27),
130
131 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
132 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
133 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
134 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
135 FATAL_ERR_DATA_OVERRUN = (1 << 12),
136 FATAL_ERR_CRC_ERR_TX = (1 << 11),
137 FATAL_ERR_CRC_ERR_RX = (1 << 10),
138 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
139 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
140
141 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
142 FATAL_ERR_PARITY_ERR_TX |
143 FATAL_ERR_PARITY_ERR_RX |
144 FATAL_ERR_DATA_UNDERRUN |
145 FATAL_ERR_DATA_OVERRUN |
146 FATAL_ERR_CRC_ERR_TX |
147 FATAL_ERR_CRC_ERR_RX |
148 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
149
150 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
151 INT_ON_FATAL_ERR = (1 << 5),
152 INT_ON_PHYRDY_CHG = (1 << 4),
153
154 INT_ON_SIGNATURE_UPDATE = (1 << 3),
155 INT_ON_SNOTIFY_UPDATE = (1 << 2),
156 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
157 INT_ON_CMD_COMPLETE = 1,
158
159 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
160 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
161
162 /*
163 * Host Control Register (HControl) bitdefs
164 */
165 HCONTROL_ONLINE_PHY_RST = (1 << 31),
166 HCONTROL_FORCE_OFFLINE = (1 << 30),
167 HCONTROL_LEGACY = (1 << 28),
168 HCONTROL_PARITY_PROT_MOD = (1 << 14),
169 HCONTROL_DPATH_PARITY = (1 << 12),
170 HCONTROL_SNOOP_ENABLE = (1 << 10),
171 HCONTROL_PMP_ATTACHED = (1 << 9),
172 HCONTROL_COPYOUT_STATFIS = (1 << 8),
173 IE_ON_FATAL_ERR = (1 << 5),
174 IE_ON_PHYRDY_CHG = (1 << 4),
175 IE_ON_SIGNATURE_UPDATE = (1 << 3),
176 IE_ON_SNOTIFY_UPDATE = (1 << 2),
177 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
178 IE_ON_CMD_COMPLETE = 1,
179
180 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
181 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
182 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
183
184 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
185 DATA_SNOOP_ENABLE_V1 = (1 << 22),
186 DATA_SNOOP_ENABLE_V2 = (1 << 28),
187 };
188
189 /*
190 * SATA Superset Registers
191 */
192 enum {
193 SSTATUS = 0,
194 SERROR = 4,
195 SCONTROL = 8,
196 SNOTIFY = 0xC,
197 };
198
199 /*
200 * Control Status Register Set
201 */
202 enum {
203 TRANSCFG = 0,
204 TRANSSTATUS = 4,
205 LINKCFG = 8,
206 LINKCFG1 = 0xC,
207 LINKCFG2 = 0x10,
208 LINKSTATUS = 0x14,
209 LINKSTATUS1 = 0x18,
210 PHYCTRLCFG = 0x1C,
211 COMMANDSTAT = 0x20,
212 };
213
214 /* TRANSCFG (transport-layer) configuration control */
215 enum {
216 TRANSCFG_RX_WATER_MARK = (1 << 4),
217 };
218
219 /* PHY (link-layer) configuration control */
220 enum {
221 PHY_BIST_ENABLE = 0x01,
222 };
223
224 /*
225 * Command Header Table entry, i.e, command slot
226 * 4 Dwords per command slot, command header size == 64 Dwords.
227 */
228 struct cmdhdr_tbl_entry {
229 u32 cda;
230 u32 prde_fis_len;
231 u32 ttl;
232 u32 desc_info;
233 };
234
235 /*
236 * Description information bitdefs
237 */
238 enum {
239 CMD_DESC_RES = (1 << 11),
240 VENDOR_SPECIFIC_BIST = (1 << 10),
241 CMD_DESC_SNOOP_ENABLE = (1 << 9),
242 FPDMA_QUEUED_CMD = (1 << 8),
243 SRST_CMD = (1 << 7),
244 BIST = (1 << 6),
245 ATAPI_CMD = (1 << 5),
246 };
247
248 /*
249 * Command Descriptor
250 */
251 struct command_desc {
252 u8 cfis[8 * 4];
253 u8 sfis[8 * 4];
254 u8 acmd[4 * 4];
255 u8 fill[4 * 4];
256 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
257 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
258 };
259
260 /*
261 * Physical region table descriptor(PRD)
262 */
263
264 struct prde {
265 u32 dba;
266 u8 fill[2 * 4];
267 u32 ddc_and_ext;
268 };
269
270 /*
271 * ata_port private data
272 * This is our per-port instance data.
273 */
274 struct sata_fsl_port_priv {
275 struct cmdhdr_tbl_entry *cmdslot;
276 dma_addr_t cmdslot_paddr;
277 struct command_desc *cmdentry;
278 dma_addr_t cmdentry_paddr;
279 };
280
281 /*
282 * ata_port->host_set private data
283 */
284 struct sata_fsl_host_priv {
285 void __iomem *hcr_base;
286 void __iomem *ssr_base;
287 void __iomem *csr_base;
288 int irq;
289 int data_snoop;
290 struct device_attribute intr_coalescing;
291 struct device_attribute rx_watermark;
292 };
293
fsl_sata_set_irq_coalescing(struct ata_host * host,unsigned int count,unsigned int ticks)294 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
295 unsigned int count, unsigned int ticks)
296 {
297 struct sata_fsl_host_priv *host_priv = host->private_data;
298 void __iomem *hcr_base = host_priv->hcr_base;
299 unsigned long flags;
300
301 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
302 count = ICC_MAX_INT_COUNT_THRESHOLD;
303 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
304 count = ICC_MIN_INT_COUNT_THRESHOLD;
305
306 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
307 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
308 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
309 (count > ICC_MIN_INT_COUNT_THRESHOLD))
310 ticks = ICC_SAFE_INT_TICKS;
311
312 spin_lock_irqsave(&host->lock, flags);
313 iowrite32((count << 24 | ticks), hcr_base + ICC);
314
315 intr_coalescing_count = count;
316 intr_coalescing_ticks = ticks;
317 spin_unlock_irqrestore(&host->lock, flags);
318
319 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
320 intr_coalescing_count, intr_coalescing_ticks);
321 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
322 hcr_base, ioread32(hcr_base + ICC));
323 }
324
fsl_sata_intr_coalescing_show(struct device * dev,struct device_attribute * attr,char * buf)325 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
326 struct device_attribute *attr, char *buf)
327 {
328 return sprintf(buf, "%d %d\n",
329 intr_coalescing_count, intr_coalescing_ticks);
330 }
331
fsl_sata_intr_coalescing_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)332 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335 {
336 unsigned int coalescing_count, coalescing_ticks;
337
338 if (sscanf(buf, "%d%d",
339 &coalescing_count,
340 &coalescing_ticks) != 2) {
341 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
342 return -EINVAL;
343 }
344
345 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
346 coalescing_count, coalescing_ticks);
347
348 return strlen(buf);
349 }
350
fsl_sata_rx_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)351 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
352 struct device_attribute *attr, char *buf)
353 {
354 unsigned int rx_watermark;
355 unsigned long flags;
356 struct ata_host *host = dev_get_drvdata(dev);
357 struct sata_fsl_host_priv *host_priv = host->private_data;
358 void __iomem *csr_base = host_priv->csr_base;
359
360 spin_lock_irqsave(&host->lock, flags);
361 rx_watermark = ioread32(csr_base + TRANSCFG);
362 rx_watermark &= 0x1f;
363
364 spin_unlock_irqrestore(&host->lock, flags);
365 return sprintf(buf, "%d\n", rx_watermark);
366 }
367
fsl_sata_rx_watermark_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)368 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
369 struct device_attribute *attr,
370 const char *buf, size_t count)
371 {
372 unsigned int rx_watermark;
373 unsigned long flags;
374 struct ata_host *host = dev_get_drvdata(dev);
375 struct sata_fsl_host_priv *host_priv = host->private_data;
376 void __iomem *csr_base = host_priv->csr_base;
377 u32 temp;
378
379 if (sscanf(buf, "%d", &rx_watermark) != 1) {
380 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
381 return -EINVAL;
382 }
383
384 spin_lock_irqsave(&host->lock, flags);
385 temp = ioread32(csr_base + TRANSCFG);
386 temp &= 0xffffffe0;
387 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
388
389 spin_unlock_irqrestore(&host->lock, flags);
390 return strlen(buf);
391 }
392
sata_fsl_tag(unsigned int tag,void __iomem * hcr_base)393 static inline unsigned int sata_fsl_tag(unsigned int tag,
394 void __iomem *hcr_base)
395 {
396 /* We let libATA core do actual (queue) tag allocation */
397
398 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
399 DPRINTK("tag %d invalid : out of range\n", tag);
400 return 0;
401 }
402
403 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
404 DPRINTK("tag %d invalid : in use!!\n", tag);
405 return 0;
406 }
407
408 return tag;
409 }
410
sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv * pp,unsigned int tag,u32 desc_info,u32 data_xfer_len,u8 num_prde,u8 fis_len)411 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
412 unsigned int tag, u32 desc_info,
413 u32 data_xfer_len, u8 num_prde,
414 u8 fis_len)
415 {
416 dma_addr_t cmd_descriptor_address;
417
418 cmd_descriptor_address = pp->cmdentry_paddr +
419 tag * SATA_FSL_CMD_DESC_SIZE;
420
421 /* NOTE: both data_xfer_len & fis_len are Dword counts */
422
423 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
424 pp->cmdslot[tag].prde_fis_len =
425 cpu_to_le32((num_prde << 16) | (fis_len << 2));
426 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
427 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
428
429 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
430 pp->cmdslot[tag].cda,
431 pp->cmdslot[tag].prde_fis_len,
432 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
433
434 }
435
sata_fsl_fill_sg(struct ata_queued_cmd * qc,void * cmd_desc,u32 * ttl,dma_addr_t cmd_desc_paddr,int data_snoop)436 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
437 u32 *ttl, dma_addr_t cmd_desc_paddr,
438 int data_snoop)
439 {
440 struct scatterlist *sg;
441 unsigned int num_prde = 0;
442 u32 ttl_dwords = 0;
443
444 /*
445 * NOTE : direct & indirect prdt's are contiguously allocated
446 */
447 struct prde *prd = (struct prde *)&((struct command_desc *)
448 cmd_desc)->prdt;
449
450 struct prde *prd_ptr_to_indirect_ext = NULL;
451 unsigned indirect_ext_segment_sz = 0;
452 dma_addr_t indirect_ext_segment_paddr;
453 unsigned int si;
454
455 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
456
457 indirect_ext_segment_paddr = cmd_desc_paddr +
458 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
459
460 for_each_sg(qc->sg, sg, qc->n_elem, si) {
461 dma_addr_t sg_addr = sg_dma_address(sg);
462 u32 sg_len = sg_dma_len(sg);
463
464 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
465 (unsigned long long)sg_addr, sg_len);
466
467 /* warn if each s/g element is not dword aligned */
468 if (unlikely(sg_addr & 0x03))
469 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
470 (unsigned long long)sg_addr);
471 if (unlikely(sg_len & 0x03))
472 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
473 sg_len);
474
475 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
476 sg_next(sg) != NULL) {
477 VPRINTK("setting indirect prde\n");
478 prd_ptr_to_indirect_ext = prd;
479 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
480 indirect_ext_segment_sz = 0;
481 ++prd;
482 ++num_prde;
483 }
484
485 ttl_dwords += sg_len;
486 prd->dba = cpu_to_le32(sg_addr);
487 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
488
489 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
490 ttl_dwords, prd->dba, prd->ddc_and_ext);
491
492 ++num_prde;
493 ++prd;
494 if (prd_ptr_to_indirect_ext)
495 indirect_ext_segment_sz += sg_len;
496 }
497
498 if (prd_ptr_to_indirect_ext) {
499 /* set indirect extension flag along with indirect ext. size */
500 prd_ptr_to_indirect_ext->ddc_and_ext =
501 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
502 data_snoop |
503 (indirect_ext_segment_sz & ~0x03)));
504 }
505
506 *ttl = ttl_dwords;
507 return num_prde;
508 }
509
sata_fsl_qc_prep(struct ata_queued_cmd * qc)510 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
511 {
512 struct ata_port *ap = qc->ap;
513 struct sata_fsl_port_priv *pp = ap->private_data;
514 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
515 void __iomem *hcr_base = host_priv->hcr_base;
516 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
517 struct command_desc *cd;
518 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
519 u32 num_prde = 0;
520 u32 ttl_dwords = 0;
521 dma_addr_t cd_paddr;
522
523 cd = (struct command_desc *)pp->cmdentry + tag;
524 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
525
526 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
527
528 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
529 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
530
531 if (qc->tf.protocol == ATA_PROT_NCQ) {
532 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
533 cd->cfis[3], cd->cfis[11]);
534 }
535
536 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
537 if (ata_is_atapi(qc->tf.protocol)) {
538 desc_info |= ATAPI_CMD;
539 memset((void *)&cd->acmd, 0, 32);
540 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
541 }
542
543 if (qc->flags & ATA_QCFLAG_DMAMAP)
544 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
545 &ttl_dwords, cd_paddr,
546 host_priv->data_snoop);
547
548 if (qc->tf.protocol == ATA_PROT_NCQ)
549 desc_info |= FPDMA_QUEUED_CMD;
550
551 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
552 num_prde, 5);
553
554 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
555 desc_info, ttl_dwords, num_prde);
556
557 return AC_ERR_OK;
558 }
559
sata_fsl_qc_issue(struct ata_queued_cmd * qc)560 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
561 {
562 struct ata_port *ap = qc->ap;
563 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
564 void __iomem *hcr_base = host_priv->hcr_base;
565 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
566
567 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
568 ioread32(CQ + hcr_base),
569 ioread32(CA + hcr_base),
570 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
571
572 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
573
574 /* Simply queue command to the controller/device */
575 iowrite32(1 << tag, CQ + hcr_base);
576
577 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
578 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
579
580 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
581 ioread32(CE + hcr_base),
582 ioread32(DE + hcr_base),
583 ioread32(CC + hcr_base),
584 ioread32(COMMANDSTAT + host_priv->csr_base));
585
586 return 0;
587 }
588
sata_fsl_qc_fill_rtf(struct ata_queued_cmd * qc)589 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
590 {
591 struct sata_fsl_port_priv *pp = qc->ap->private_data;
592 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
593 void __iomem *hcr_base = host_priv->hcr_base;
594 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
595 struct command_desc *cd;
596
597 cd = pp->cmdentry + tag;
598
599 ata_tf_from_fis(cd->sfis, &qc->result_tf);
600 return true;
601 }
602
sata_fsl_scr_write(struct ata_link * link,unsigned int sc_reg_in,u32 val)603 static int sata_fsl_scr_write(struct ata_link *link,
604 unsigned int sc_reg_in, u32 val)
605 {
606 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
607 void __iomem *ssr_base = host_priv->ssr_base;
608 unsigned int sc_reg;
609
610 switch (sc_reg_in) {
611 case SCR_STATUS:
612 case SCR_ERROR:
613 case SCR_CONTROL:
614 case SCR_ACTIVE:
615 sc_reg = sc_reg_in;
616 break;
617 default:
618 return -EINVAL;
619 }
620
621 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
622
623 iowrite32(val, ssr_base + (sc_reg * 4));
624 return 0;
625 }
626
sata_fsl_scr_read(struct ata_link * link,unsigned int sc_reg_in,u32 * val)627 static int sata_fsl_scr_read(struct ata_link *link,
628 unsigned int sc_reg_in, u32 *val)
629 {
630 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
631 void __iomem *ssr_base = host_priv->ssr_base;
632 unsigned int sc_reg;
633
634 switch (sc_reg_in) {
635 case SCR_STATUS:
636 case SCR_ERROR:
637 case SCR_CONTROL:
638 case SCR_ACTIVE:
639 sc_reg = sc_reg_in;
640 break;
641 default:
642 return -EINVAL;
643 }
644
645 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
646
647 *val = ioread32(ssr_base + (sc_reg * 4));
648 return 0;
649 }
650
sata_fsl_freeze(struct ata_port * ap)651 static void sata_fsl_freeze(struct ata_port *ap)
652 {
653 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
654 void __iomem *hcr_base = host_priv->hcr_base;
655 u32 temp;
656
657 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
658 ioread32(CQ + hcr_base),
659 ioread32(CA + hcr_base),
660 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
661 VPRINTK("CmdStat = 0x%x\n",
662 ioread32(host_priv->csr_base + COMMANDSTAT));
663
664 /* disable interrupts on the controller/port */
665 temp = ioread32(hcr_base + HCONTROL);
666 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
667
668 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
669 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
670 }
671
sata_fsl_thaw(struct ata_port * ap)672 static void sata_fsl_thaw(struct ata_port *ap)
673 {
674 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
675 void __iomem *hcr_base = host_priv->hcr_base;
676 u32 temp;
677
678 /* ack. any pending IRQs for this controller/port */
679 temp = ioread32(hcr_base + HSTATUS);
680
681 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
682
683 if (temp & 0x3F)
684 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
685
686 /* enable interrupts on the controller/port */
687 temp = ioread32(hcr_base + HCONTROL);
688 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
689
690 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
691 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
692 }
693
sata_fsl_pmp_attach(struct ata_port * ap)694 static void sata_fsl_pmp_attach(struct ata_port *ap)
695 {
696 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
697 void __iomem *hcr_base = host_priv->hcr_base;
698 u32 temp;
699
700 temp = ioread32(hcr_base + HCONTROL);
701 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
702 }
703
sata_fsl_pmp_detach(struct ata_port * ap)704 static void sata_fsl_pmp_detach(struct ata_port *ap)
705 {
706 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
707 void __iomem *hcr_base = host_priv->hcr_base;
708 u32 temp;
709
710 temp = ioread32(hcr_base + HCONTROL);
711 temp &= ~HCONTROL_PMP_ATTACHED;
712 iowrite32(temp, hcr_base + HCONTROL);
713
714 /* enable interrupts on the controller/port */
715 temp = ioread32(hcr_base + HCONTROL);
716 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
717
718 }
719
sata_fsl_port_start(struct ata_port * ap)720 static int sata_fsl_port_start(struct ata_port *ap)
721 {
722 struct device *dev = ap->host->dev;
723 struct sata_fsl_port_priv *pp;
724 void *mem;
725 dma_addr_t mem_dma;
726 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
727 void __iomem *hcr_base = host_priv->hcr_base;
728 u32 temp;
729
730 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
731 if (!pp)
732 return -ENOMEM;
733
734 mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
735 GFP_KERNEL);
736 if (!mem) {
737 kfree(pp);
738 return -ENOMEM;
739 }
740
741 pp->cmdslot = mem;
742 pp->cmdslot_paddr = mem_dma;
743
744 mem += SATA_FSL_CMD_SLOT_SIZE;
745 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
746
747 pp->cmdentry = mem;
748 pp->cmdentry_paddr = mem_dma;
749
750 ap->private_data = pp;
751
752 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
753 pp->cmdslot_paddr, pp->cmdentry_paddr);
754
755 /* Now, update the CHBA register in host controller cmd register set */
756 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
757
758 /*
759 * Now, we can bring the controller on-line & also initiate
760 * the COMINIT sequence, we simply return here and the boot-probing
761 * & device discovery process is re-initiated by libATA using a
762 * Softreset EH (dummy) session. Hence, boot probing and device
763 * discovey will be part of sata_fsl_softreset() callback.
764 */
765
766 temp = ioread32(hcr_base + HCONTROL);
767 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
768
769 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
770 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
771 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
772
773 return 0;
774 }
775
sata_fsl_port_stop(struct ata_port * ap)776 static void sata_fsl_port_stop(struct ata_port *ap)
777 {
778 struct device *dev = ap->host->dev;
779 struct sata_fsl_port_priv *pp = ap->private_data;
780 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
781 void __iomem *hcr_base = host_priv->hcr_base;
782 u32 temp;
783
784 /*
785 * Force host controller to go off-line, aborting current operations
786 */
787 temp = ioread32(hcr_base + HCONTROL);
788 temp &= ~HCONTROL_ONLINE_PHY_RST;
789 temp |= HCONTROL_FORCE_OFFLINE;
790 iowrite32(temp, hcr_base + HCONTROL);
791
792 /* Poll for controller to go offline - should happen immediately */
793 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
794
795 ap->private_data = NULL;
796 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
797 pp->cmdslot, pp->cmdslot_paddr);
798
799 kfree(pp);
800 }
801
sata_fsl_dev_classify(struct ata_port * ap)802 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
803 {
804 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
805 void __iomem *hcr_base = host_priv->hcr_base;
806 struct ata_taskfile tf;
807 u32 temp;
808
809 temp = ioread32(hcr_base + SIGNATURE);
810
811 VPRINTK("raw sig = 0x%x\n", temp);
812 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
813 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
814
815 tf.lbah = (temp >> 24) & 0xff;
816 tf.lbam = (temp >> 16) & 0xff;
817 tf.lbal = (temp >> 8) & 0xff;
818 tf.nsect = temp & 0xff;
819
820 return ata_dev_classify(&tf);
821 }
822
sata_fsl_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)823 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
824 unsigned long deadline)
825 {
826 struct ata_port *ap = link->ap;
827 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
828 void __iomem *hcr_base = host_priv->hcr_base;
829 u32 temp;
830 int i = 0;
831 unsigned long start_jiffies;
832
833 DPRINTK("in xx_hardreset\n");
834
835 try_offline_again:
836 /*
837 * Force host controller to go off-line, aborting current operations
838 */
839 temp = ioread32(hcr_base + HCONTROL);
840 temp &= ~HCONTROL_ONLINE_PHY_RST;
841 iowrite32(temp, hcr_base + HCONTROL);
842
843 /* Poll for controller to go offline */
844 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
845 1, 500);
846
847 if (temp & ONLINE) {
848 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
849
850 /*
851 * Try to offline controller atleast twice
852 */
853 i++;
854 if (i == 2)
855 goto err;
856 else
857 goto try_offline_again;
858 }
859
860 DPRINTK("hardreset, controller off-lined\n");
861 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
862 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
863
864 /*
865 * PHY reset should remain asserted for atleast 1ms
866 */
867 ata_msleep(ap, 1);
868
869 sata_set_spd(link);
870
871 /*
872 * Now, bring the host controller online again, this can take time
873 * as PHY reset and communication establishment, 1st D2H FIS and
874 * device signature update is done, on safe side assume 500ms
875 * NOTE : Host online status may be indicated immediately!!
876 */
877
878 temp = ioread32(hcr_base + HCONTROL);
879 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
880 temp |= HCONTROL_PMP_ATTACHED;
881 iowrite32(temp, hcr_base + HCONTROL);
882
883 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
884
885 if (!(temp & ONLINE)) {
886 ata_port_err(ap, "Hardreset failed, not on-lined\n");
887 goto err;
888 }
889
890 DPRINTK("hardreset, controller off-lined & on-lined\n");
891 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
892 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
893
894 /*
895 * First, wait for the PHYRDY change to occur before waiting for
896 * the signature, and also verify if SStatus indicates device
897 * presence
898 */
899
900 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
901 if ((!(temp & 0x10)) || ata_link_offline(link)) {
902 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
903 ioread32(hcr_base + HSTATUS));
904 *class = ATA_DEV_NONE;
905 return 0;
906 }
907
908 /*
909 * Wait for the first D2H from device,i.e,signature update notification
910 */
911 start_jiffies = jiffies;
912 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
913 500, jiffies_to_msecs(deadline - start_jiffies));
914
915 if ((temp & 0xFF) != 0x18) {
916 ata_port_warn(ap, "No Signature Update\n");
917 *class = ATA_DEV_NONE;
918 goto do_followup_srst;
919 } else {
920 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
921 jiffies_to_msecs(jiffies - start_jiffies));
922 *class = sata_fsl_dev_classify(ap);
923 return 0;
924 }
925
926 do_followup_srst:
927 /*
928 * request libATA to perform follow-up softreset
929 */
930 return -EAGAIN;
931
932 err:
933 return -EIO;
934 }
935
sata_fsl_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)936 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
937 unsigned long deadline)
938 {
939 struct ata_port *ap = link->ap;
940 struct sata_fsl_port_priv *pp = ap->private_data;
941 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
942 void __iomem *hcr_base = host_priv->hcr_base;
943 int pmp = sata_srst_pmp(link);
944 u32 temp;
945 struct ata_taskfile tf;
946 u8 *cfis;
947 u32 Serror;
948
949 DPRINTK("in xx_softreset\n");
950
951 if (ata_link_offline(link)) {
952 DPRINTK("PHY reports no device\n");
953 *class = ATA_DEV_NONE;
954 return 0;
955 }
956
957 /*
958 * Send a device reset (SRST) explicitly on command slot #0
959 * Check : will the command queue (reg) be cleared during offlining ??
960 * Also we will be online only if Phy commn. has been established
961 * and device presence has been detected, therefore if we have
962 * reached here, we can send a command to the target device
963 */
964
965 DPRINTK("Sending SRST/device reset\n");
966
967 ata_tf_init(link->device, &tf);
968 cfis = (u8 *) &pp->cmdentry->cfis;
969
970 /* device reset/SRST is a control register update FIS, uses tag0 */
971 sata_fsl_setup_cmd_hdr_entry(pp, 0,
972 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
973
974 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
975 ata_tf_to_fis(&tf, pmp, 0, cfis);
976
977 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
978 cfis[0], cfis[1], cfis[2], cfis[3]);
979
980 /*
981 * Queue SRST command to the controller/device, ensure that no
982 * other commands are active on the controller/device
983 */
984
985 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
986 ioread32(CQ + hcr_base),
987 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
988
989 iowrite32(0xFFFF, CC + hcr_base);
990 if (pmp != SATA_PMP_CTRL_PORT)
991 iowrite32(pmp, CQPMP + hcr_base);
992 iowrite32(1, CQ + hcr_base);
993
994 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
995 if (temp & 0x1) {
996 ata_port_warn(ap, "ATA_SRST issue failed\n");
997
998 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
999 ioread32(CQ + hcr_base),
1000 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1001
1002 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1003
1004 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1005 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1006 DPRINTK("Serror = 0x%x\n", Serror);
1007 goto err;
1008 }
1009
1010 ata_msleep(ap, 1);
1011
1012 /*
1013 * SATA device enters reset state after receiving a Control register
1014 * FIS with SRST bit asserted and it awaits another H2D Control reg.
1015 * FIS with SRST bit cleared, then the device does internal diags &
1016 * initialization, followed by indicating it's initialization status
1017 * using ATA signature D2H register FIS to the host controller.
1018 */
1019
1020 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1021 0, 0, 5);
1022
1023 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
1024 ata_tf_to_fis(&tf, pmp, 0, cfis);
1025
1026 if (pmp != SATA_PMP_CTRL_PORT)
1027 iowrite32(pmp, CQPMP + hcr_base);
1028 iowrite32(1, CQ + hcr_base);
1029 ata_msleep(ap, 150); /* ?? */
1030
1031 /*
1032 * The above command would have signalled an interrupt on command
1033 * complete, which needs special handling, by clearing the Nth
1034 * command bit of the CCreg
1035 */
1036 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1037
1038 DPRINTK("SATA FSL : Now checking device signature\n");
1039
1040 *class = ATA_DEV_NONE;
1041
1042 /* Verify if SStatus indicates device presence */
1043 if (ata_link_online(link)) {
1044 /*
1045 * if we are here, device presence has been detected,
1046 * 1st D2H FIS would have been received, but sfis in
1047 * command desc. is not updated, but signature register
1048 * would have been updated
1049 */
1050
1051 *class = sata_fsl_dev_classify(ap);
1052
1053 DPRINTK("class = %d\n", *class);
1054 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1055 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1056 }
1057
1058 return 0;
1059
1060 err:
1061 return -EIO;
1062 }
1063
sata_fsl_error_handler(struct ata_port * ap)1064 static void sata_fsl_error_handler(struct ata_port *ap)
1065 {
1066
1067 DPRINTK("in xx_error_handler\n");
1068 sata_pmp_error_handler(ap);
1069
1070 }
1071
sata_fsl_post_internal_cmd(struct ata_queued_cmd * qc)1072 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1073 {
1074 if (qc->flags & ATA_QCFLAG_FAILED)
1075 qc->err_mask |= AC_ERR_OTHER;
1076
1077 if (qc->err_mask) {
1078 /* make DMA engine forget about the failed command */
1079
1080 }
1081 }
1082
sata_fsl_error_intr(struct ata_port * ap)1083 static void sata_fsl_error_intr(struct ata_port *ap)
1084 {
1085 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1086 void __iomem *hcr_base = host_priv->hcr_base;
1087 u32 hstatus, dereg=0, cereg = 0, SError = 0;
1088 unsigned int err_mask = 0, action = 0;
1089 int freeze = 0, abort=0;
1090 struct ata_link *link = NULL;
1091 struct ata_queued_cmd *qc = NULL;
1092 struct ata_eh_info *ehi;
1093
1094 hstatus = ioread32(hcr_base + HSTATUS);
1095 cereg = ioread32(hcr_base + CE);
1096
1097 /* first, analyze and record host port events */
1098 link = &ap->link;
1099 ehi = &link->eh_info;
1100 ata_ehi_clear_desc(ehi);
1101
1102 /*
1103 * Handle & Clear SError
1104 */
1105
1106 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1107 if (unlikely(SError & 0xFFFF0000))
1108 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1109
1110 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1111 hstatus, cereg, ioread32(hcr_base + DE), SError);
1112
1113 /* handle fatal errors */
1114 if (hstatus & FATAL_ERROR_DECODE) {
1115 ehi->err_mask |= AC_ERR_ATA_BUS;
1116 ehi->action |= ATA_EH_SOFTRESET;
1117
1118 freeze = 1;
1119 }
1120
1121 /* Handle SDB FIS receive & notify update */
1122 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1123 sata_async_notification(ap);
1124
1125 /* Handle PHYRDY change notification */
1126 if (hstatus & INT_ON_PHYRDY_CHG) {
1127 DPRINTK("SATA FSL: PHYRDY change indication\n");
1128
1129 /* Setup a soft-reset EH action */
1130 ata_ehi_hotplugged(ehi);
1131 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1132 freeze = 1;
1133 }
1134
1135 /* handle single device errors */
1136 if (cereg) {
1137 /*
1138 * clear the command error, also clears queue to the device
1139 * in error, and we can (re)issue commands to this device.
1140 * When a device is in error all commands queued into the
1141 * host controller and at the device are considered aborted
1142 * and the queue for that device is stopped. Now, after
1143 * clearing the device error, we can issue commands to the
1144 * device to interrogate it to find the source of the error.
1145 */
1146 abort = 1;
1147
1148 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1149 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1150
1151 /* find out the offending link and qc */
1152 if (ap->nr_pmp_links) {
1153 unsigned int dev_num;
1154
1155 dereg = ioread32(hcr_base + DE);
1156 iowrite32(dereg, hcr_base + DE);
1157 iowrite32(cereg, hcr_base + CE);
1158
1159 dev_num = ffs(dereg) - 1;
1160 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1161 link = &ap->pmp_link[dev_num];
1162 ehi = &link->eh_info;
1163 qc = ata_qc_from_tag(ap, link->active_tag);
1164 /*
1165 * We should consider this as non fatal error,
1166 * and TF must be updated as done below.
1167 */
1168
1169 err_mask |= AC_ERR_DEV;
1170
1171 } else {
1172 err_mask |= AC_ERR_HSM;
1173 action |= ATA_EH_HARDRESET;
1174 freeze = 1;
1175 }
1176 } else {
1177 dereg = ioread32(hcr_base + DE);
1178 iowrite32(dereg, hcr_base + DE);
1179 iowrite32(cereg, hcr_base + CE);
1180
1181 qc = ata_qc_from_tag(ap, link->active_tag);
1182 /*
1183 * We should consider this as non fatal error,
1184 * and TF must be updated as done below.
1185 */
1186 err_mask |= AC_ERR_DEV;
1187 }
1188 }
1189
1190 /* record error info */
1191 if (qc)
1192 qc->err_mask |= err_mask;
1193 else
1194 ehi->err_mask |= err_mask;
1195
1196 ehi->action |= action;
1197
1198 /* freeze or abort */
1199 if (freeze)
1200 ata_port_freeze(ap);
1201 else if (abort) {
1202 if (qc)
1203 ata_link_abort(qc->dev->link);
1204 else
1205 ata_port_abort(ap);
1206 }
1207 }
1208
sata_fsl_host_intr(struct ata_port * ap)1209 static void sata_fsl_host_intr(struct ata_port *ap)
1210 {
1211 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1212 void __iomem *hcr_base = host_priv->hcr_base;
1213 u32 hstatus, done_mask = 0;
1214 struct ata_queued_cmd *qc;
1215 u32 SError;
1216 u32 tag;
1217 u32 status_mask = INT_ON_ERROR;
1218
1219 hstatus = ioread32(hcr_base + HSTATUS);
1220
1221 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1222
1223 /* Read command completed register */
1224 done_mask = ioread32(hcr_base + CC);
1225
1226 /* Workaround for data length mismatch errata */
1227 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1228 ata_qc_for_each_with_internal(ap, qc, tag) {
1229 if (qc && ata_is_atapi(qc->tf.protocol)) {
1230 u32 hcontrol;
1231 /* Set HControl[27] to clear error registers */
1232 hcontrol = ioread32(hcr_base + HCONTROL);
1233 iowrite32(hcontrol | CLEAR_ERROR,
1234 hcr_base + HCONTROL);
1235
1236 /* Clear HControl[27] */
1237 iowrite32(hcontrol & ~CLEAR_ERROR,
1238 hcr_base + HCONTROL);
1239
1240 /* Clear SError[E] bit */
1241 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1242 SError);
1243
1244 /* Ignore fatal error and device error */
1245 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1246 | INT_ON_FATAL_ERR);
1247 break;
1248 }
1249 }
1250 }
1251
1252 if (unlikely(SError & 0xFFFF0000)) {
1253 DPRINTK("serror @host_intr : 0x%x\n", SError);
1254 sata_fsl_error_intr(ap);
1255 }
1256
1257 if (unlikely(hstatus & status_mask)) {
1258 DPRINTK("error interrupt!!\n");
1259 sata_fsl_error_intr(ap);
1260 return;
1261 }
1262
1263 VPRINTK("Status of all queues :\n");
1264 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
1265 done_mask,
1266 ioread32(hcr_base + CA),
1267 ioread32(hcr_base + CE),
1268 ioread32(hcr_base + CQ),
1269 ap->qc_active);
1270
1271 if (done_mask & ap->qc_active) {
1272 int i;
1273 /* clear CC bit, this will also complete the interrupt */
1274 iowrite32(done_mask, hcr_base + CC);
1275
1276 DPRINTK("Status of all queues :\n");
1277 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1278 done_mask, ioread32(hcr_base + CA),
1279 ioread32(hcr_base + CE));
1280
1281 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1282 if (done_mask & (1 << i))
1283 DPRINTK
1284 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1285 i, ioread32(hcr_base + CC),
1286 ioread32(hcr_base + CA));
1287 }
1288 ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
1289 return;
1290
1291 } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
1292 iowrite32(1, hcr_base + CC);
1293 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1294
1295 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1296 ioread32(hcr_base + CC));
1297
1298 if (qc) {
1299 ata_qc_complete(qc);
1300 }
1301 } else {
1302 /* Spurious Interrupt!! */
1303 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1304 ioread32(hcr_base + CC));
1305 iowrite32(done_mask, hcr_base + CC);
1306 return;
1307 }
1308 }
1309
sata_fsl_interrupt(int irq,void * dev_instance)1310 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1311 {
1312 struct ata_host *host = dev_instance;
1313 struct sata_fsl_host_priv *host_priv = host->private_data;
1314 void __iomem *hcr_base = host_priv->hcr_base;
1315 u32 interrupt_enables;
1316 unsigned handled = 0;
1317 struct ata_port *ap;
1318
1319 /* ack. any pending IRQs for this controller/port */
1320 interrupt_enables = ioread32(hcr_base + HSTATUS);
1321 interrupt_enables &= 0x3F;
1322
1323 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1324
1325 if (!interrupt_enables)
1326 return IRQ_NONE;
1327
1328 spin_lock(&host->lock);
1329
1330 /* Assuming one port per host controller */
1331
1332 ap = host->ports[0];
1333 if (ap) {
1334 sata_fsl_host_intr(ap);
1335 } else {
1336 dev_warn(host->dev, "interrupt on disabled port 0\n");
1337 }
1338
1339 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1340 handled = 1;
1341
1342 spin_unlock(&host->lock);
1343
1344 return IRQ_RETVAL(handled);
1345 }
1346
1347 /*
1348 * Multiple ports are represented by multiple SATA controllers with
1349 * one port per controller
1350 */
sata_fsl_init_controller(struct ata_host * host)1351 static int sata_fsl_init_controller(struct ata_host *host)
1352 {
1353 struct sata_fsl_host_priv *host_priv = host->private_data;
1354 void __iomem *hcr_base = host_priv->hcr_base;
1355 u32 temp;
1356
1357 /*
1358 * NOTE : We cannot bring the controller online before setting
1359 * the CHBA, hence main controller initialization is done as
1360 * part of the port_start() callback
1361 */
1362
1363 /* sata controller to operate in enterprise mode */
1364 temp = ioread32(hcr_base + HCONTROL);
1365 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1366
1367 /* ack. any pending IRQs for this controller/port */
1368 temp = ioread32(hcr_base + HSTATUS);
1369 if (temp & 0x3F)
1370 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1371
1372 /* Keep interrupts disabled on the controller */
1373 temp = ioread32(hcr_base + HCONTROL);
1374 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1375
1376 /* Disable interrupt coalescing control(icc), for the moment */
1377 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1378 iowrite32(0x01000000, hcr_base + ICC);
1379
1380 /* clear error registers, SError is cleared by libATA */
1381 iowrite32(0x00000FFFF, hcr_base + CE);
1382 iowrite32(0x00000FFFF, hcr_base + DE);
1383
1384 /*
1385 * reset the number of command complete bits which will cause the
1386 * interrupt to be signaled
1387 */
1388 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1389 intr_coalescing_ticks);
1390
1391 /*
1392 * host controller will be brought on-line, during xx_port_start()
1393 * callback, that should also initiate the OOB, COMINIT sequence
1394 */
1395
1396 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1397 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1398
1399 return 0;
1400 }
1401
1402 /*
1403 * scsi mid-layer and libata interface structures
1404 */
1405 static struct scsi_host_template sata_fsl_sht = {
1406 ATA_NCQ_SHT("sata_fsl"),
1407 .can_queue = SATA_FSL_QUEUE_DEPTH,
1408 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1409 .dma_boundary = ATA_DMA_BOUNDARY,
1410 };
1411
1412 static struct ata_port_operations sata_fsl_ops = {
1413 .inherits = &sata_pmp_port_ops,
1414
1415 .qc_defer = ata_std_qc_defer,
1416 .qc_prep = sata_fsl_qc_prep,
1417 .qc_issue = sata_fsl_qc_issue,
1418 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1419
1420 .scr_read = sata_fsl_scr_read,
1421 .scr_write = sata_fsl_scr_write,
1422
1423 .freeze = sata_fsl_freeze,
1424 .thaw = sata_fsl_thaw,
1425 .softreset = sata_fsl_softreset,
1426 .hardreset = sata_fsl_hardreset,
1427 .pmp_softreset = sata_fsl_softreset,
1428 .error_handler = sata_fsl_error_handler,
1429 .post_internal_cmd = sata_fsl_post_internal_cmd,
1430
1431 .port_start = sata_fsl_port_start,
1432 .port_stop = sata_fsl_port_stop,
1433
1434 .pmp_attach = sata_fsl_pmp_attach,
1435 .pmp_detach = sata_fsl_pmp_detach,
1436 };
1437
1438 static const struct ata_port_info sata_fsl_port_info[] = {
1439 {
1440 .flags = SATA_FSL_HOST_FLAGS,
1441 .pio_mask = ATA_PIO4,
1442 .udma_mask = ATA_UDMA6,
1443 .port_ops = &sata_fsl_ops,
1444 },
1445 };
1446
sata_fsl_probe(struct platform_device * ofdev)1447 static int sata_fsl_probe(struct platform_device *ofdev)
1448 {
1449 int retval = -ENXIO;
1450 void __iomem *hcr_base = NULL;
1451 void __iomem *ssr_base = NULL;
1452 void __iomem *csr_base = NULL;
1453 struct sata_fsl_host_priv *host_priv = NULL;
1454 int irq;
1455 struct ata_host *host = NULL;
1456 u32 temp;
1457
1458 struct ata_port_info pi = sata_fsl_port_info[0];
1459 const struct ata_port_info *ppi[] = { &pi, NULL };
1460
1461 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1462
1463 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1464 if (!hcr_base)
1465 goto error_exit_with_cleanup;
1466
1467 ssr_base = hcr_base + 0x100;
1468 csr_base = hcr_base + 0x140;
1469
1470 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1471 temp = ioread32(csr_base + TRANSCFG);
1472 temp = temp & 0xffffffe0;
1473 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1474 }
1475
1476 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1477 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1478 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1479
1480 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1481 if (!host_priv)
1482 goto error_exit_with_cleanup;
1483
1484 host_priv->hcr_base = hcr_base;
1485 host_priv->ssr_base = ssr_base;
1486 host_priv->csr_base = csr_base;
1487
1488 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1489 if (!irq) {
1490 dev_err(&ofdev->dev, "invalid irq from platform\n");
1491 goto error_exit_with_cleanup;
1492 }
1493 host_priv->irq = irq;
1494
1495 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1496 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1497 else
1498 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1499
1500 /* allocate host structure */
1501 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1502 if (!host) {
1503 retval = -ENOMEM;
1504 goto error_exit_with_cleanup;
1505 }
1506
1507 /* host->iomap is not used currently */
1508 host->private_data = host_priv;
1509
1510 /* initialize host controller */
1511 sata_fsl_init_controller(host);
1512
1513 /*
1514 * Now, register with libATA core, this will also initiate the
1515 * device discovery process, invoking our port_start() handler &
1516 * error_handler() to execute a dummy Softreset EH session
1517 */
1518 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1519 &sata_fsl_sht);
1520
1521 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1522 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1523 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1524 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1525 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1526 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1527 if (retval)
1528 goto error_exit_with_cleanup;
1529
1530 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1531 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1532 sysfs_attr_init(&host_priv->rx_watermark.attr);
1533 host_priv->rx_watermark.attr.name = "rx_watermark";
1534 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1535 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1536 if (retval) {
1537 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1538 goto error_exit_with_cleanup;
1539 }
1540
1541 return 0;
1542
1543 error_exit_with_cleanup:
1544
1545 if (host)
1546 ata_host_detach(host);
1547
1548 if (hcr_base)
1549 iounmap(hcr_base);
1550 kfree(host_priv);
1551
1552 return retval;
1553 }
1554
sata_fsl_remove(struct platform_device * ofdev)1555 static int sata_fsl_remove(struct platform_device *ofdev)
1556 {
1557 struct ata_host *host = platform_get_drvdata(ofdev);
1558 struct sata_fsl_host_priv *host_priv = host->private_data;
1559
1560 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1561 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1562
1563 ata_host_detach(host);
1564
1565 irq_dispose_mapping(host_priv->irq);
1566 iounmap(host_priv->hcr_base);
1567 kfree(host_priv);
1568
1569 return 0;
1570 }
1571
1572 #ifdef CONFIG_PM_SLEEP
sata_fsl_suspend(struct platform_device * op,pm_message_t state)1573 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1574 {
1575 struct ata_host *host = platform_get_drvdata(op);
1576 return ata_host_suspend(host, state);
1577 }
1578
sata_fsl_resume(struct platform_device * op)1579 static int sata_fsl_resume(struct platform_device *op)
1580 {
1581 struct ata_host *host = platform_get_drvdata(op);
1582 struct sata_fsl_host_priv *host_priv = host->private_data;
1583 int ret;
1584 void __iomem *hcr_base = host_priv->hcr_base;
1585 struct ata_port *ap = host->ports[0];
1586 struct sata_fsl_port_priv *pp = ap->private_data;
1587
1588 ret = sata_fsl_init_controller(host);
1589 if (ret) {
1590 dev_err(&op->dev, "Error initializing hardware\n");
1591 return ret;
1592 }
1593
1594 /* Recovery the CHBA register in host controller cmd register set */
1595 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1596
1597 iowrite32((ioread32(hcr_base + HCONTROL)
1598 | HCONTROL_ONLINE_PHY_RST
1599 | HCONTROL_SNOOP_ENABLE
1600 | HCONTROL_PMP_ATTACHED),
1601 hcr_base + HCONTROL);
1602
1603 ata_host_resume(host);
1604 return 0;
1605 }
1606 #endif
1607
1608 static const struct of_device_id fsl_sata_match[] = {
1609 {
1610 .compatible = "fsl,pq-sata",
1611 },
1612 {
1613 .compatible = "fsl,pq-sata-v2",
1614 },
1615 {},
1616 };
1617
1618 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1619
1620 static struct platform_driver fsl_sata_driver = {
1621 .driver = {
1622 .name = "fsl-sata",
1623 .of_match_table = fsl_sata_match,
1624 },
1625 .probe = sata_fsl_probe,
1626 .remove = sata_fsl_remove,
1627 #ifdef CONFIG_PM_SLEEP
1628 .suspend = sata_fsl_suspend,
1629 .resume = sata_fsl_resume,
1630 #endif
1631 };
1632
1633 module_platform_driver(fsl_sata_driver);
1634
1635 MODULE_LICENSE("GPL");
1636 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1637 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1638 MODULE_VERSION("1.10");
1639