1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Mikael Pettersson
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/driver-api/libata.rst
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_PCI_CTL = 0x48, /* PCI control/status reg */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
63 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
64
65 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
66 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
67 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
68 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
69 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
70 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
71 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
72 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
73 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
74 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
75 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
76 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
77
78 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
79 PDC_SATA_ERROR = 0x04,
80 PDC_PHYMODE4 = 0x14,
81 PDC_LINK_LAYER_ERRORS = 0x6C,
82 PDC_FPDMA_CTLSTAT = 0xD8,
83 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
84 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
85
86 /* PDC_FPDMA_CTLSTAT bit definitions */
87 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
88 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
89 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
90
91 /* PDC_GLOBAL_CTL bit definitions */
92 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
93 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
94 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
95 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
96 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
97 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
98 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
99 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
100 PDC_DRIVE_ERR = (1 << 21), /* drive error */
101 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
102 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
103 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
104 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
105 PDC2_ATA_DMA_CNT_ERR,
106 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
107 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
108 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
109 PDC1_ERR_MASK | PDC2_ERR_MASK,
110
111 board_2037x = 0, /* FastTrak S150 TX2plus */
112 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
113 board_20319 = 2, /* FastTrak S150 TX4 */
114 board_20619 = 3, /* FastTrak TX4000 */
115 board_2057x = 4, /* SATAII150 Tx2plus */
116 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
117 board_40518 = 6, /* SATAII150 Tx4 */
118
119 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
120
121 /* Sequence counter control registers bit definitions */
122 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
123
124 /* Feature register values */
125 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
126 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
127
128 /* Device/Head register values */
129 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
130
131 /* PDC_CTLSTAT bit definitions */
132 PDC_DMA_ENABLE = (1 << 7),
133 PDC_IRQ_DISABLE = (1 << 10),
134 PDC_RESET = (1 << 11), /* HDMA reset */
135
136 PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING,
137
138 /* ap->flags bits */
139 PDC_FLAG_GEN_II = (1 << 24),
140 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
141 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
142 };
143
144 struct pdc_port_priv {
145 u8 *pkt;
146 dma_addr_t pkt_dma;
147 };
148
149 struct pdc_host_priv {
150 spinlock_t hard_reset_lock;
151 };
152
153 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
154 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
155 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
156 static int pdc_common_port_start(struct ata_port *ap);
157 static int pdc_sata_port_start(struct ata_port *ap);
158 static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc);
159 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
160 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
161 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
162 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
163 static void pdc_irq_clear(struct ata_port *ap);
164 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
165 static void pdc_freeze(struct ata_port *ap);
166 static void pdc_sata_freeze(struct ata_port *ap);
167 static void pdc_thaw(struct ata_port *ap);
168 static void pdc_sata_thaw(struct ata_port *ap);
169 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
170 unsigned long deadline);
171 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
172 unsigned long deadline);
173 static void pdc_error_handler(struct ata_port *ap);
174 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
175 static int pdc_pata_cable_detect(struct ata_port *ap);
176 static int pdc_sata_cable_detect(struct ata_port *ap);
177
178 static struct scsi_host_template pdc_ata_sht = {
179 ATA_BASE_SHT(DRV_NAME),
180 .sg_tablesize = PDC_MAX_PRD,
181 .dma_boundary = ATA_DMA_BOUNDARY,
182 };
183
184 static const struct ata_port_operations pdc_common_ops = {
185 .inherits = &ata_sff_port_ops,
186
187 .sff_tf_load = pdc_tf_load_mmio,
188 .sff_exec_command = pdc_exec_command_mmio,
189 .check_atapi_dma = pdc_check_atapi_dma,
190 .qc_prep = pdc_qc_prep,
191 .qc_issue = pdc_qc_issue,
192
193 .sff_irq_clear = pdc_irq_clear,
194 .lost_interrupt = ATA_OP_NULL,
195
196 .post_internal_cmd = pdc_post_internal_cmd,
197 .error_handler = pdc_error_handler,
198 };
199
200 static struct ata_port_operations pdc_sata_ops = {
201 .inherits = &pdc_common_ops,
202 .cable_detect = pdc_sata_cable_detect,
203 .freeze = pdc_sata_freeze,
204 .thaw = pdc_sata_thaw,
205 .scr_read = pdc_sata_scr_read,
206 .scr_write = pdc_sata_scr_write,
207 .port_start = pdc_sata_port_start,
208 .hardreset = pdc_sata_hardreset,
209 };
210
211 /* First-generation chips need a more restrictive ->check_atapi_dma op,
212 and ->freeze/thaw that ignore the hotplug controls. */
213 static struct ata_port_operations pdc_old_sata_ops = {
214 .inherits = &pdc_sata_ops,
215 .freeze = pdc_freeze,
216 .thaw = pdc_thaw,
217 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
218 };
219
220 static struct ata_port_operations pdc_pata_ops = {
221 .inherits = &pdc_common_ops,
222 .cable_detect = pdc_pata_cable_detect,
223 .freeze = pdc_freeze,
224 .thaw = pdc_thaw,
225 .port_start = pdc_common_port_start,
226 .softreset = pdc_pata_softreset,
227 };
228
229 static const struct ata_port_info pdc_port_info[] = {
230 [board_2037x] =
231 {
232 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
233 PDC_FLAG_SATA_PATA,
234 .pio_mask = ATA_PIO4,
235 .mwdma_mask = ATA_MWDMA2,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &pdc_old_sata_ops,
238 },
239
240 [board_2037x_pata] =
241 {
242 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
243 .pio_mask = ATA_PIO4,
244 .mwdma_mask = ATA_MWDMA2,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &pdc_pata_ops,
247 },
248
249 [board_20319] =
250 {
251 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
252 PDC_FLAG_4_PORTS,
253 .pio_mask = ATA_PIO4,
254 .mwdma_mask = ATA_MWDMA2,
255 .udma_mask = ATA_UDMA6,
256 .port_ops = &pdc_old_sata_ops,
257 },
258
259 [board_20619] =
260 {
261 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
262 PDC_FLAG_4_PORTS,
263 .pio_mask = ATA_PIO4,
264 .mwdma_mask = ATA_MWDMA2,
265 .udma_mask = ATA_UDMA6,
266 .port_ops = &pdc_pata_ops,
267 },
268
269 [board_2057x] =
270 {
271 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
272 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
273 .pio_mask = ATA_PIO4,
274 .mwdma_mask = ATA_MWDMA2,
275 .udma_mask = ATA_UDMA6,
276 .port_ops = &pdc_sata_ops,
277 },
278
279 [board_2057x_pata] =
280 {
281 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
282 PDC_FLAG_GEN_II,
283 .pio_mask = ATA_PIO4,
284 .mwdma_mask = ATA_MWDMA2,
285 .udma_mask = ATA_UDMA6,
286 .port_ops = &pdc_pata_ops,
287 },
288
289 [board_40518] =
290 {
291 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
292 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
293 .pio_mask = ATA_PIO4,
294 .mwdma_mask = ATA_MWDMA2,
295 .udma_mask = ATA_UDMA6,
296 .port_ops = &pdc_sata_ops,
297 },
298 };
299
300 static const struct pci_device_id pdc_ata_pci_tbl[] = {
301 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
302 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
303 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
304 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
305 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
306 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
307 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
308 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
309 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
310 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
311
312 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
313 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
314 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
315 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
316 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
317 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
318
319 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
320
321 { } /* terminate list */
322 };
323
324 static struct pci_driver pdc_ata_pci_driver = {
325 .name = DRV_NAME,
326 .id_table = pdc_ata_pci_tbl,
327 .probe = pdc_ata_init_one,
328 .remove = ata_pci_remove_one,
329 };
330
pdc_common_port_start(struct ata_port * ap)331 static int pdc_common_port_start(struct ata_port *ap)
332 {
333 struct device *dev = ap->host->dev;
334 struct pdc_port_priv *pp;
335 int rc;
336
337 /* we use the same prd table as bmdma, allocate it */
338 rc = ata_bmdma_port_start(ap);
339 if (rc)
340 return rc;
341
342 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
343 if (!pp)
344 return -ENOMEM;
345
346 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
347 if (!pp->pkt)
348 return -ENOMEM;
349
350 ap->private_data = pp;
351
352 return 0;
353 }
354
pdc_sata_port_start(struct ata_port * ap)355 static int pdc_sata_port_start(struct ata_port *ap)
356 {
357 int rc;
358
359 rc = pdc_common_port_start(ap);
360 if (rc)
361 return rc;
362
363 /* fix up PHYMODE4 align timing */
364 if (ap->flags & PDC_FLAG_GEN_II) {
365 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
366 unsigned int tmp;
367
368 tmp = readl(sata_mmio + PDC_PHYMODE4);
369 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
370 writel(tmp, sata_mmio + PDC_PHYMODE4);
371 }
372
373 return 0;
374 }
375
pdc_fpdma_clear_interrupt_flag(struct ata_port * ap)376 static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
377 {
378 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
379 u32 tmp;
380
381 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
382 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
383 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
384
385 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
386 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
387 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
388 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
389 }
390
pdc_fpdma_reset(struct ata_port * ap)391 static void pdc_fpdma_reset(struct ata_port *ap)
392 {
393 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
394 u8 tmp;
395
396 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
397 tmp &= 0x7F;
398 tmp |= PDC_FPDMA_CTLSTAT_RESET;
399 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
400 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
401 udelay(100);
402 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
403 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
404 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
405
406 pdc_fpdma_clear_interrupt_flag(ap);
407 }
408
pdc_not_at_command_packet_phase(struct ata_port * ap)409 static void pdc_not_at_command_packet_phase(struct ata_port *ap)
410 {
411 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
412 unsigned int i;
413 u32 tmp;
414
415 /* check not at ASIC packet command phase */
416 for (i = 0; i < 100; ++i) {
417 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
418 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
419 if ((tmp & 0xF) != 1)
420 break;
421 udelay(100);
422 }
423 }
424
pdc_clear_internal_debug_record_error_register(struct ata_port * ap)425 static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
426 {
427 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
428
429 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
430 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
431 }
432
pdc_reset_port(struct ata_port * ap)433 static void pdc_reset_port(struct ata_port *ap)
434 {
435 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
436 unsigned int i;
437 u32 tmp;
438
439 if (ap->flags & PDC_FLAG_GEN_II)
440 pdc_not_at_command_packet_phase(ap);
441
442 tmp = readl(ata_ctlstat_mmio);
443 tmp |= PDC_RESET;
444 writel(tmp, ata_ctlstat_mmio);
445
446 for (i = 11; i > 0; i--) {
447 tmp = readl(ata_ctlstat_mmio);
448 if (tmp & PDC_RESET)
449 break;
450
451 udelay(100);
452
453 tmp |= PDC_RESET;
454 writel(tmp, ata_ctlstat_mmio);
455 }
456
457 tmp &= ~PDC_RESET;
458 writel(tmp, ata_ctlstat_mmio);
459 readl(ata_ctlstat_mmio); /* flush */
460
461 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
462 pdc_fpdma_reset(ap);
463 pdc_clear_internal_debug_record_error_register(ap);
464 }
465 }
466
pdc_pata_cable_detect(struct ata_port * ap)467 static int pdc_pata_cable_detect(struct ata_port *ap)
468 {
469 u8 tmp;
470 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
471
472 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
473 if (tmp & 0x01)
474 return ATA_CBL_PATA40;
475 return ATA_CBL_PATA80;
476 }
477
pdc_sata_cable_detect(struct ata_port * ap)478 static int pdc_sata_cable_detect(struct ata_port *ap)
479 {
480 return ATA_CBL_SATA;
481 }
482
pdc_sata_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)483 static int pdc_sata_scr_read(struct ata_link *link,
484 unsigned int sc_reg, u32 *val)
485 {
486 if (sc_reg > SCR_CONTROL)
487 return -EINVAL;
488 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
489 return 0;
490 }
491
pdc_sata_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)492 static int pdc_sata_scr_write(struct ata_link *link,
493 unsigned int sc_reg, u32 val)
494 {
495 if (sc_reg > SCR_CONTROL)
496 return -EINVAL;
497 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
498 return 0;
499 }
500
pdc_atapi_pkt(struct ata_queued_cmd * qc)501 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
502 {
503 struct ata_port *ap = qc->ap;
504 dma_addr_t sg_table = ap->bmdma_prd_dma;
505 unsigned int cdb_len = qc->dev->cdb_len;
506 u8 *cdb = qc->cdb;
507 struct pdc_port_priv *pp = ap->private_data;
508 u8 *buf = pp->pkt;
509 __le32 *buf32 = (__le32 *) buf;
510 unsigned int dev_sel, feature;
511
512 /* set control bits (byte 0), zero delay seq id (byte 3),
513 * and seq id (byte 2)
514 */
515 switch (qc->tf.protocol) {
516 case ATAPI_PROT_DMA:
517 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
518 buf32[0] = cpu_to_le32(PDC_PKT_READ);
519 else
520 buf32[0] = 0;
521 break;
522 case ATAPI_PROT_NODATA:
523 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
524 break;
525 default:
526 BUG();
527 break;
528 }
529 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
530 buf32[2] = 0; /* no next-packet */
531
532 /* select drive */
533 if (sata_scr_valid(&ap->link))
534 dev_sel = PDC_DEVICE_SATA;
535 else
536 dev_sel = qc->tf.device;
537
538 buf[12] = (1 << 5) | ATA_REG_DEVICE;
539 buf[13] = dev_sel;
540 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
541 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
542
543 buf[16] = (1 << 5) | ATA_REG_NSECT;
544 buf[17] = qc->tf.nsect;
545 buf[18] = (1 << 5) | ATA_REG_LBAL;
546 buf[19] = qc->tf.lbal;
547
548 /* set feature and byte counter registers */
549 if (qc->tf.protocol != ATAPI_PROT_DMA)
550 feature = PDC_FEATURE_ATAPI_PIO;
551 else
552 feature = PDC_FEATURE_ATAPI_DMA;
553
554 buf[20] = (1 << 5) | ATA_REG_FEATURE;
555 buf[21] = feature;
556 buf[22] = (1 << 5) | ATA_REG_BYTEL;
557 buf[23] = qc->tf.lbam;
558 buf[24] = (1 << 5) | ATA_REG_BYTEH;
559 buf[25] = qc->tf.lbah;
560
561 /* send ATAPI packet command 0xA0 */
562 buf[26] = (1 << 5) | ATA_REG_CMD;
563 buf[27] = qc->tf.command;
564
565 /* select drive and check DRQ */
566 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
567 buf[29] = dev_sel;
568
569 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
570 BUG_ON(cdb_len & ~0x1E);
571
572 /* append the CDB as the final part */
573 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
574 memcpy(buf+31, cdb, cdb_len);
575 }
576
577 /**
578 * pdc_fill_sg - Fill PCI IDE PRD table
579 * @qc: Metadata associated with taskfile to be transferred
580 *
581 * Fill PCI IDE PRD (scatter-gather) table with segments
582 * associated with the current disk command.
583 * Make sure hardware does not choke on it.
584 *
585 * LOCKING:
586 * spin_lock_irqsave(host lock)
587 *
588 */
pdc_fill_sg(struct ata_queued_cmd * qc)589 static void pdc_fill_sg(struct ata_queued_cmd *qc)
590 {
591 struct ata_port *ap = qc->ap;
592 struct ata_bmdma_prd *prd = ap->bmdma_prd;
593 struct scatterlist *sg;
594 const u32 SG_COUNT_ASIC_BUG = 41*4;
595 unsigned int si, idx;
596 u32 len;
597
598 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
599 return;
600
601 idx = 0;
602 for_each_sg(qc->sg, sg, qc->n_elem, si) {
603 u32 addr, offset;
604 u32 sg_len;
605
606 /* determine if physical DMA addr spans 64K boundary.
607 * Note h/w doesn't support 64-bit, so we unconditionally
608 * truncate dma_addr_t to u32.
609 */
610 addr = (u32) sg_dma_address(sg);
611 sg_len = sg_dma_len(sg);
612
613 while (sg_len) {
614 offset = addr & 0xffff;
615 len = sg_len;
616 if ((offset + sg_len) > 0x10000)
617 len = 0x10000 - offset;
618
619 prd[idx].addr = cpu_to_le32(addr);
620 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
621 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
622
623 idx++;
624 sg_len -= len;
625 addr += len;
626 }
627 }
628
629 len = le32_to_cpu(prd[idx - 1].flags_len);
630
631 if (len > SG_COUNT_ASIC_BUG) {
632 u32 addr;
633
634 VPRINTK("Splitting last PRD.\n");
635
636 addr = le32_to_cpu(prd[idx - 1].addr);
637 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
638 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
639
640 addr = addr + len - SG_COUNT_ASIC_BUG;
641 len = SG_COUNT_ASIC_BUG;
642 prd[idx].addr = cpu_to_le32(addr);
643 prd[idx].flags_len = cpu_to_le32(len);
644 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
645
646 idx++;
647 }
648
649 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
650 }
651
pdc_qc_prep(struct ata_queued_cmd * qc)652 static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc)
653 {
654 struct pdc_port_priv *pp = qc->ap->private_data;
655 unsigned int i;
656
657 VPRINTK("ENTER\n");
658
659 switch (qc->tf.protocol) {
660 case ATA_PROT_DMA:
661 pdc_fill_sg(qc);
662 /*FALLTHROUGH*/
663 case ATA_PROT_NODATA:
664 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
665 qc->dev->devno, pp->pkt);
666 if (qc->tf.flags & ATA_TFLAG_LBA48)
667 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
668 else
669 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
670 pdc_pkt_footer(&qc->tf, pp->pkt, i);
671 break;
672 case ATAPI_PROT_PIO:
673 pdc_fill_sg(qc);
674 break;
675 case ATAPI_PROT_DMA:
676 pdc_fill_sg(qc);
677 /*FALLTHROUGH*/
678 case ATAPI_PROT_NODATA:
679 pdc_atapi_pkt(qc);
680 break;
681 default:
682 break;
683 }
684
685 return AC_ERR_OK;
686 }
687
pdc_is_sataii_tx4(unsigned long flags)688 static int pdc_is_sataii_tx4(unsigned long flags)
689 {
690 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
691 return (flags & mask) == mask;
692 }
693
pdc_port_no_to_ata_no(unsigned int port_no,int is_sataii_tx4)694 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
695 int is_sataii_tx4)
696 {
697 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
698 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
699 }
700
pdc_sata_nr_ports(const struct ata_port * ap)701 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
702 {
703 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
704 }
705
pdc_sata_ata_port_to_ata_no(const struct ata_port * ap)706 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
707 {
708 const struct ata_host *host = ap->host;
709 unsigned int nr_ports = pdc_sata_nr_ports(ap);
710 unsigned int i;
711
712 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
713 ;
714 BUG_ON(i >= nr_ports);
715 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
716 }
717
pdc_freeze(struct ata_port * ap)718 static void pdc_freeze(struct ata_port *ap)
719 {
720 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
721 u32 tmp;
722
723 tmp = readl(ata_mmio + PDC_CTLSTAT);
724 tmp |= PDC_IRQ_DISABLE;
725 tmp &= ~PDC_DMA_ENABLE;
726 writel(tmp, ata_mmio + PDC_CTLSTAT);
727 readl(ata_mmio + PDC_CTLSTAT); /* flush */
728 }
729
pdc_sata_freeze(struct ata_port * ap)730 static void pdc_sata_freeze(struct ata_port *ap)
731 {
732 struct ata_host *host = ap->host;
733 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
734 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
735 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
736 u32 hotplug_status;
737
738 /* Disable hotplug events on this port.
739 *
740 * Locking:
741 * 1) hotplug register accesses must be serialised via host->lock
742 * 2) ap->lock == &ap->host->lock
743 * 3) ->freeze() and ->thaw() are called with ap->lock held
744 */
745 hotplug_status = readl(host_mmio + hotplug_offset);
746 hotplug_status |= 0x11 << (ata_no + 16);
747 writel(hotplug_status, host_mmio + hotplug_offset);
748 readl(host_mmio + hotplug_offset); /* flush */
749
750 pdc_freeze(ap);
751 }
752
pdc_thaw(struct ata_port * ap)753 static void pdc_thaw(struct ata_port *ap)
754 {
755 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
756 u32 tmp;
757
758 /* clear IRQ */
759 readl(ata_mmio + PDC_COMMAND);
760
761 /* turn IRQ back on */
762 tmp = readl(ata_mmio + PDC_CTLSTAT);
763 tmp &= ~PDC_IRQ_DISABLE;
764 writel(tmp, ata_mmio + PDC_CTLSTAT);
765 readl(ata_mmio + PDC_CTLSTAT); /* flush */
766 }
767
pdc_sata_thaw(struct ata_port * ap)768 static void pdc_sata_thaw(struct ata_port *ap)
769 {
770 struct ata_host *host = ap->host;
771 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
772 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
773 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
774 u32 hotplug_status;
775
776 pdc_thaw(ap);
777
778 /* Enable hotplug events on this port.
779 * Locking: see pdc_sata_freeze().
780 */
781 hotplug_status = readl(host_mmio + hotplug_offset);
782 hotplug_status |= 0x11 << ata_no;
783 hotplug_status &= ~(0x11 << (ata_no + 16));
784 writel(hotplug_status, host_mmio + hotplug_offset);
785 readl(host_mmio + hotplug_offset); /* flush */
786 }
787
pdc_pata_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)788 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
789 unsigned long deadline)
790 {
791 pdc_reset_port(link->ap);
792 return ata_sff_softreset(link, class, deadline);
793 }
794
pdc_ata_port_to_ata_no(const struct ata_port * ap)795 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
796 {
797 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
798 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
799
800 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
801 return (ata_mmio - host_mmio - 0x200) / 0x80;
802 }
803
pdc_hard_reset_port(struct ata_port * ap)804 static void pdc_hard_reset_port(struct ata_port *ap)
805 {
806 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
807 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
808 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
809 struct pdc_host_priv *hpriv = ap->host->private_data;
810 u8 tmp;
811
812 spin_lock(&hpriv->hard_reset_lock);
813
814 tmp = readb(pcictl_b1_mmio);
815 tmp &= ~(0x10 << ata_no);
816 writeb(tmp, pcictl_b1_mmio);
817 readb(pcictl_b1_mmio); /* flush */
818 udelay(100);
819 tmp |= (0x10 << ata_no);
820 writeb(tmp, pcictl_b1_mmio);
821 readb(pcictl_b1_mmio); /* flush */
822
823 spin_unlock(&hpriv->hard_reset_lock);
824 }
825
pdc_sata_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)826 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
827 unsigned long deadline)
828 {
829 if (link->ap->flags & PDC_FLAG_GEN_II)
830 pdc_not_at_command_packet_phase(link->ap);
831 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
832 pdc_hard_reset_port(link->ap);
833 pdc_reset_port(link->ap);
834
835 /* sata_promise can't reliably acquire the first D2H Reg FIS
836 * after hardreset. Do non-waiting hardreset and request
837 * follow-up SRST.
838 */
839 return sata_std_hardreset(link, class, deadline);
840 }
841
pdc_error_handler(struct ata_port * ap)842 static void pdc_error_handler(struct ata_port *ap)
843 {
844 if (!(ap->pflags & ATA_PFLAG_FROZEN))
845 pdc_reset_port(ap);
846
847 ata_sff_error_handler(ap);
848 }
849
pdc_post_internal_cmd(struct ata_queued_cmd * qc)850 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
851 {
852 struct ata_port *ap = qc->ap;
853
854 /* make DMA engine forget about the failed command */
855 if (qc->flags & ATA_QCFLAG_FAILED)
856 pdc_reset_port(ap);
857 }
858
pdc_error_intr(struct ata_port * ap,struct ata_queued_cmd * qc,u32 port_status,u32 err_mask)859 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
860 u32 port_status, u32 err_mask)
861 {
862 struct ata_eh_info *ehi = &ap->link.eh_info;
863 unsigned int ac_err_mask = 0;
864
865 ata_ehi_clear_desc(ehi);
866 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
867 port_status &= err_mask;
868
869 if (port_status & PDC_DRIVE_ERR)
870 ac_err_mask |= AC_ERR_DEV;
871 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
872 ac_err_mask |= AC_ERR_OTHER;
873 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
874 ac_err_mask |= AC_ERR_ATA_BUS;
875 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
876 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
877 ac_err_mask |= AC_ERR_HOST_BUS;
878
879 if (sata_scr_valid(&ap->link)) {
880 u32 serror;
881
882 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
883 ehi->serror |= serror;
884 }
885
886 qc->err_mask |= ac_err_mask;
887
888 pdc_reset_port(ap);
889
890 ata_port_abort(ap);
891 }
892
pdc_host_intr(struct ata_port * ap,struct ata_queued_cmd * qc)893 static unsigned int pdc_host_intr(struct ata_port *ap,
894 struct ata_queued_cmd *qc)
895 {
896 unsigned int handled = 0;
897 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
898 u32 port_status, err_mask;
899
900 err_mask = PDC_ERR_MASK;
901 if (ap->flags & PDC_FLAG_GEN_II)
902 err_mask &= ~PDC1_ERR_MASK;
903 else
904 err_mask &= ~PDC2_ERR_MASK;
905 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
906 if (unlikely(port_status & err_mask)) {
907 pdc_error_intr(ap, qc, port_status, err_mask);
908 return 1;
909 }
910
911 switch (qc->tf.protocol) {
912 case ATA_PROT_DMA:
913 case ATA_PROT_NODATA:
914 case ATAPI_PROT_DMA:
915 case ATAPI_PROT_NODATA:
916 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
917 ata_qc_complete(qc);
918 handled = 1;
919 break;
920 default:
921 ap->stats.idle_irq++;
922 break;
923 }
924
925 return handled;
926 }
927
pdc_irq_clear(struct ata_port * ap)928 static void pdc_irq_clear(struct ata_port *ap)
929 {
930 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
931
932 readl(ata_mmio + PDC_COMMAND);
933 }
934
pdc_interrupt(int irq,void * dev_instance)935 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
936 {
937 struct ata_host *host = dev_instance;
938 struct ata_port *ap;
939 u32 mask = 0;
940 unsigned int i, tmp;
941 unsigned int handled = 0;
942 void __iomem *host_mmio;
943 unsigned int hotplug_offset, ata_no;
944 u32 hotplug_status;
945 int is_sataii_tx4;
946
947 VPRINTK("ENTER\n");
948
949 if (!host || !host->iomap[PDC_MMIO_BAR]) {
950 VPRINTK("QUICK EXIT\n");
951 return IRQ_NONE;
952 }
953
954 host_mmio = host->iomap[PDC_MMIO_BAR];
955
956 spin_lock(&host->lock);
957
958 /* read and clear hotplug flags for all ports */
959 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
960 hotplug_offset = PDC2_SATA_PLUG_CSR;
961 hotplug_status = readl(host_mmio + hotplug_offset);
962 if (hotplug_status & 0xff)
963 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
964 hotplug_status &= 0xff; /* clear uninteresting bits */
965 } else
966 hotplug_status = 0;
967
968 /* reading should also clear interrupts */
969 mask = readl(host_mmio + PDC_INT_SEQMASK);
970
971 if (mask == 0xffffffff && hotplug_status == 0) {
972 VPRINTK("QUICK EXIT 2\n");
973 goto done_irq;
974 }
975
976 mask &= 0xffff; /* only 16 SEQIDs possible */
977 if (mask == 0 && hotplug_status == 0) {
978 VPRINTK("QUICK EXIT 3\n");
979 goto done_irq;
980 }
981
982 writel(mask, host_mmio + PDC_INT_SEQMASK);
983
984 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
985
986 for (i = 0; i < host->n_ports; i++) {
987 VPRINTK("port %u\n", i);
988 ap = host->ports[i];
989
990 /* check for a plug or unplug event */
991 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
992 tmp = hotplug_status & (0x11 << ata_no);
993 if (tmp) {
994 struct ata_eh_info *ehi = &ap->link.eh_info;
995 ata_ehi_clear_desc(ehi);
996 ata_ehi_hotplugged(ehi);
997 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
998 ata_port_freeze(ap);
999 ++handled;
1000 continue;
1001 }
1002
1003 /* check for a packet interrupt */
1004 tmp = mask & (1 << (i + 1));
1005 if (tmp) {
1006 struct ata_queued_cmd *qc;
1007
1008 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1009 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1010 handled += pdc_host_intr(ap, qc);
1011 }
1012 }
1013
1014 VPRINTK("EXIT\n");
1015
1016 done_irq:
1017 spin_unlock(&host->lock);
1018 return IRQ_RETVAL(handled);
1019 }
1020
pdc_packet_start(struct ata_queued_cmd * qc)1021 static void pdc_packet_start(struct ata_queued_cmd *qc)
1022 {
1023 struct ata_port *ap = qc->ap;
1024 struct pdc_port_priv *pp = ap->private_data;
1025 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1026 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1027 unsigned int port_no = ap->port_no;
1028 u8 seq = (u8) (port_no + 1);
1029
1030 VPRINTK("ENTER, ap %p\n", ap);
1031
1032 writel(0x00000001, host_mmio + (seq * 4));
1033 readl(host_mmio + (seq * 4)); /* flush */
1034
1035 pp->pkt[2] = seq;
1036 wmb(); /* flush PRD, pkt writes */
1037 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1038 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1039 }
1040
pdc_qc_issue(struct ata_queued_cmd * qc)1041 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1042 {
1043 switch (qc->tf.protocol) {
1044 case ATAPI_PROT_NODATA:
1045 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1046 break;
1047 /*FALLTHROUGH*/
1048 case ATA_PROT_NODATA:
1049 if (qc->tf.flags & ATA_TFLAG_POLLING)
1050 break;
1051 /*FALLTHROUGH*/
1052 case ATAPI_PROT_DMA:
1053 case ATA_PROT_DMA:
1054 pdc_packet_start(qc);
1055 return 0;
1056 default:
1057 break;
1058 }
1059 return ata_sff_qc_issue(qc);
1060 }
1061
pdc_tf_load_mmio(struct ata_port * ap,const struct ata_taskfile * tf)1062 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1063 {
1064 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1065 ata_sff_tf_load(ap, tf);
1066 }
1067
pdc_exec_command_mmio(struct ata_port * ap,const struct ata_taskfile * tf)1068 static void pdc_exec_command_mmio(struct ata_port *ap,
1069 const struct ata_taskfile *tf)
1070 {
1071 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1072 ata_sff_exec_command(ap, tf);
1073 }
1074
pdc_check_atapi_dma(struct ata_queued_cmd * qc)1075 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1076 {
1077 u8 *scsicmd = qc->scsicmd->cmnd;
1078 int pio = 1; /* atapi dma off by default */
1079
1080 /* Whitelist commands that may use DMA. */
1081 switch (scsicmd[0]) {
1082 case WRITE_12:
1083 case WRITE_10:
1084 case WRITE_6:
1085 case READ_12:
1086 case READ_10:
1087 case READ_6:
1088 case 0xad: /* READ_DVD_STRUCTURE */
1089 case 0xbe: /* READ_CD */
1090 pio = 0;
1091 }
1092 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1093 if (scsicmd[0] == WRITE_10) {
1094 unsigned int lba =
1095 (scsicmd[2] << 24) |
1096 (scsicmd[3] << 16) |
1097 (scsicmd[4] << 8) |
1098 scsicmd[5];
1099 if (lba >= 0xFFFF4FA2)
1100 pio = 1;
1101 }
1102 return pio;
1103 }
1104
pdc_old_sata_check_atapi_dma(struct ata_queued_cmd * qc)1105 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1106 {
1107 /* First generation chips cannot use ATAPI DMA on SATA ports */
1108 return 1;
1109 }
1110
pdc_ata_setup_port(struct ata_port * ap,void __iomem * base,void __iomem * scr_addr)1111 static void pdc_ata_setup_port(struct ata_port *ap,
1112 void __iomem *base, void __iomem *scr_addr)
1113 {
1114 ap->ioaddr.cmd_addr = base;
1115 ap->ioaddr.data_addr = base;
1116 ap->ioaddr.feature_addr =
1117 ap->ioaddr.error_addr = base + 0x4;
1118 ap->ioaddr.nsect_addr = base + 0x8;
1119 ap->ioaddr.lbal_addr = base + 0xc;
1120 ap->ioaddr.lbam_addr = base + 0x10;
1121 ap->ioaddr.lbah_addr = base + 0x14;
1122 ap->ioaddr.device_addr = base + 0x18;
1123 ap->ioaddr.command_addr =
1124 ap->ioaddr.status_addr = base + 0x1c;
1125 ap->ioaddr.altstatus_addr =
1126 ap->ioaddr.ctl_addr = base + 0x38;
1127 ap->ioaddr.scr_addr = scr_addr;
1128 }
1129
pdc_host_init(struct ata_host * host)1130 static void pdc_host_init(struct ata_host *host)
1131 {
1132 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1133 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1134 int hotplug_offset;
1135 u32 tmp;
1136
1137 if (is_gen2)
1138 hotplug_offset = PDC2_SATA_PLUG_CSR;
1139 else
1140 hotplug_offset = PDC_SATA_PLUG_CSR;
1141
1142 /*
1143 * Except for the hotplug stuff, this is voodoo from the
1144 * Promise driver. Label this entire section
1145 * "TODO: figure out why we do this"
1146 */
1147
1148 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1149 tmp = readl(host_mmio + PDC_FLASH_CTL);
1150 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1151 if (!is_gen2)
1152 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1153 writel(tmp, host_mmio + PDC_FLASH_CTL);
1154
1155 /* clear plug/unplug flags for all ports */
1156 tmp = readl(host_mmio + hotplug_offset);
1157 writel(tmp | 0xff, host_mmio + hotplug_offset);
1158
1159 tmp = readl(host_mmio + hotplug_offset);
1160 if (is_gen2) /* unmask plug/unplug ints */
1161 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1162 else /* mask plug/unplug ints */
1163 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1164
1165 /* don't initialise TBG or SLEW on 2nd generation chips */
1166 if (is_gen2)
1167 return;
1168
1169 /* reduce TBG clock to 133 Mhz. */
1170 tmp = readl(host_mmio + PDC_TBG_MODE);
1171 tmp &= ~0x30000; /* clear bit 17, 16*/
1172 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1173 writel(tmp, host_mmio + PDC_TBG_MODE);
1174
1175 readl(host_mmio + PDC_TBG_MODE); /* flush */
1176 msleep(10);
1177
1178 /* adjust slew rate control register. */
1179 tmp = readl(host_mmio + PDC_SLEW_CTL);
1180 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1181 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1182 writel(tmp, host_mmio + PDC_SLEW_CTL);
1183 }
1184
pdc_ata_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1185 static int pdc_ata_init_one(struct pci_dev *pdev,
1186 const struct pci_device_id *ent)
1187 {
1188 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1189 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1190 struct ata_host *host;
1191 struct pdc_host_priv *hpriv;
1192 void __iomem *host_mmio;
1193 int n_ports, i, rc;
1194 int is_sataii_tx4;
1195
1196 ata_print_version_once(&pdev->dev, DRV_VERSION);
1197
1198 /* enable and acquire resources */
1199 rc = pcim_enable_device(pdev);
1200 if (rc)
1201 return rc;
1202
1203 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1204 if (rc == -EBUSY)
1205 pcim_pin_device(pdev);
1206 if (rc)
1207 return rc;
1208 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1209
1210 /* determine port configuration and setup host */
1211 n_ports = 2;
1212 if (pi->flags & PDC_FLAG_4_PORTS)
1213 n_ports = 4;
1214 for (i = 0; i < n_ports; i++)
1215 ppi[i] = pi;
1216
1217 if (pi->flags & PDC_FLAG_SATA_PATA) {
1218 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1219 if (!(tmp & 0x80))
1220 ppi[n_ports++] = pi + 1;
1221 }
1222
1223 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1224 if (!host) {
1225 dev_err(&pdev->dev, "failed to allocate host\n");
1226 return -ENOMEM;
1227 }
1228 hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL);
1229 if (!hpriv)
1230 return -ENOMEM;
1231 spin_lock_init(&hpriv->hard_reset_lock);
1232 host->private_data = hpriv;
1233 host->iomap = pcim_iomap_table(pdev);
1234
1235 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1236 for (i = 0; i < host->n_ports; i++) {
1237 struct ata_port *ap = host->ports[i];
1238 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1239 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1240 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1241
1242 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1243
1244 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1245 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1246 }
1247
1248 /* initialize adapter */
1249 pdc_host_init(host);
1250
1251 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
1252 if (rc)
1253 return rc;
1254 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
1255 if (rc)
1256 return rc;
1257
1258 /* start host, request IRQ and attach */
1259 pci_set_master(pdev);
1260 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1261 &pdc_ata_sht);
1262 }
1263
1264 module_pci_driver(pdc_ata_pci_driver);
1265
1266 MODULE_AUTHOR("Jeff Garzik");
1267 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1268 MODULE_LICENSE("GPL");
1269 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1270 MODULE_VERSION(DRV_VERSION);
1271