1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 * Fabien Dessenne <fabien.dessenne@st.com>
8 * Mickael Reulier <mickael.reulier@st.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/component.h>
13 #include <linux/of_address.h>
14 #include <linux/of_graph.h>
15 #include <linux/reset.h>
16
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_of.h>
24 #include <drm/drm_bridge.h>
25 #include <drm/drm_plane_helper.h>
26
27 #include <video/videomode.h>
28
29 #include "ltdc.h"
30
31 #define NB_CRTC 1
32 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
33
34 #define MAX_IRQ 4
35
36 #define MAX_ENDPOINTS 2
37
38 #define HWVER_10200 0x010200
39 #define HWVER_10300 0x010300
40 #define HWVER_20101 0x020101
41
42 /*
43 * The address of some registers depends on the HW version: such registers have
44 * an extra offset specified with reg_ofs.
45 */
46 #define REG_OFS_NONE 0
47 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
48 #define REG_OFS (ldev->caps.reg_ofs)
49 #define LAY_OFS 0x80 /* Register Offset between 2 layers */
50
51 /* Global register offsets */
52 #define LTDC_IDR 0x0000 /* IDentification */
53 #define LTDC_LCR 0x0004 /* Layer Count */
54 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
55 #define LTDC_BPCR 0x000C /* Back Porch Configuration */
56 #define LTDC_AWCR 0x0010 /* Active Width Configuration */
57 #define LTDC_TWCR 0x0014 /* Total Width Configuration */
58 #define LTDC_GCR 0x0018 /* Global Control */
59 #define LTDC_GC1R 0x001C /* Global Configuration 1 */
60 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */
61 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
62 #define LTDC_GACR 0x0028 /* GAmma Correction */
63 #define LTDC_BCCR 0x002C /* Background Color Configuration */
64 #define LTDC_IER 0x0034 /* Interrupt Enable */
65 #define LTDC_ISR 0x0038 /* Interrupt Status */
66 #define LTDC_ICR 0x003C /* Interrupt Clear */
67 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
68 #define LTDC_CPSR 0x0044 /* Current Position Status */
69 #define LTDC_CDSR 0x0048 /* Current Display Status */
70
71 /* Layer register offsets */
72 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
73 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
74 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
75 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
76 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
77 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
78 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
79 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
80 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
81 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
82 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
83 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
84 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
85 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
86 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
87 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
88 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
89 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
90 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
91 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
92 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
93
94 /* Bit definitions */
95 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
96 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
97
98 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
99 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
100
101 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
102 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
103
104 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
105 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
106
107 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
108 #define GCR_DEN BIT(16) /* Dither ENable */
109 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
110 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
111 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
112 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
113
114 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
115 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
116 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
117 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
118 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
119 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
120 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
121 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
122 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
123 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
124 #define GC1R_TP BIT(25) /* Timing Programmable */
125 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
126 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
127 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
128 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
129 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
130
131 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
132 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
133 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
134 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
135 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
136 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
137
138 #define SRCR_IMR BIT(0) /* IMmediate Reload */
139 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
140
141 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
142 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
143 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
144 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
145 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
146
147 #define IER_LIE BIT(0) /* Line Interrupt Enable */
148 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
149 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
150 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
151
152 #define ISR_LIF BIT(0) /* Line Interrupt Flag */
153 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
154 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
155 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
156
157 #define LXCR_LEN BIT(0) /* Layer ENable */
158 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
159 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
160
161 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
162 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
163
164 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
165 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
166
167 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
168
169 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
170
171 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
172 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
173
174 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
175 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
176
177 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
178
179 #define CLUT_SIZE 256
180
181 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
182 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
183 #define BF1_CA 0x400 /* Constant Alpha */
184 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
185 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
186
187 #define NB_PF 8 /* Max nb of HW pixel format */
188
189 enum ltdc_pix_fmt {
190 PF_NONE,
191 /* RGB formats */
192 PF_ARGB8888, /* ARGB [32 bits] */
193 PF_RGBA8888, /* RGBA [32 bits] */
194 PF_RGB888, /* RGB [24 bits] */
195 PF_RGB565, /* RGB [16 bits] */
196 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
197 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
198 /* Indexed formats */
199 PF_L8, /* Indexed 8 bits [8 bits] */
200 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
201 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
202 };
203
204 /* The index gives the encoding of the pixel format for an HW version */
205 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
206 PF_ARGB8888, /* 0x00 */
207 PF_RGB888, /* 0x01 */
208 PF_RGB565, /* 0x02 */
209 PF_ARGB1555, /* 0x03 */
210 PF_ARGB4444, /* 0x04 */
211 PF_L8, /* 0x05 */
212 PF_AL44, /* 0x06 */
213 PF_AL88 /* 0x07 */
214 };
215
216 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
217 PF_ARGB8888, /* 0x00 */
218 PF_RGB888, /* 0x01 */
219 PF_RGB565, /* 0x02 */
220 PF_RGBA8888, /* 0x03 */
221 PF_AL44, /* 0x04 */
222 PF_L8, /* 0x05 */
223 PF_ARGB1555, /* 0x06 */
224 PF_ARGB4444 /* 0x07 */
225 };
226
reg_read(void __iomem * base,u32 reg)227 static inline u32 reg_read(void __iomem *base, u32 reg)
228 {
229 return readl_relaxed(base + reg);
230 }
231
reg_write(void __iomem * base,u32 reg,u32 val)232 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
233 {
234 writel_relaxed(val, base + reg);
235 }
236
reg_set(void __iomem * base,u32 reg,u32 mask)237 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
238 {
239 reg_write(base, reg, reg_read(base, reg) | mask);
240 }
241
reg_clear(void __iomem * base,u32 reg,u32 mask)242 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
243 {
244 reg_write(base, reg, reg_read(base, reg) & ~mask);
245 }
246
reg_update_bits(void __iomem * base,u32 reg,u32 mask,u32 val)247 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
248 u32 val)
249 {
250 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
251 }
252
crtc_to_ltdc(struct drm_crtc * crtc)253 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
254 {
255 return (struct ltdc_device *)crtc->dev->dev_private;
256 }
257
plane_to_ltdc(struct drm_plane * plane)258 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
259 {
260 return (struct ltdc_device *)plane->dev->dev_private;
261 }
262
encoder_to_ltdc(struct drm_encoder * enc)263 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
264 {
265 return (struct ltdc_device *)enc->dev->dev_private;
266 }
267
to_ltdc_pixelformat(u32 drm_fmt)268 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
269 {
270 enum ltdc_pix_fmt pf;
271
272 switch (drm_fmt) {
273 case DRM_FORMAT_ARGB8888:
274 case DRM_FORMAT_XRGB8888:
275 pf = PF_ARGB8888;
276 break;
277 case DRM_FORMAT_RGBA8888:
278 case DRM_FORMAT_RGBX8888:
279 pf = PF_RGBA8888;
280 break;
281 case DRM_FORMAT_RGB888:
282 pf = PF_RGB888;
283 break;
284 case DRM_FORMAT_RGB565:
285 pf = PF_RGB565;
286 break;
287 case DRM_FORMAT_ARGB1555:
288 case DRM_FORMAT_XRGB1555:
289 pf = PF_ARGB1555;
290 break;
291 case DRM_FORMAT_ARGB4444:
292 case DRM_FORMAT_XRGB4444:
293 pf = PF_ARGB4444;
294 break;
295 case DRM_FORMAT_C8:
296 pf = PF_L8;
297 break;
298 default:
299 pf = PF_NONE;
300 break;
301 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
302 }
303
304 return pf;
305 }
306
to_drm_pixelformat(enum ltdc_pix_fmt pf)307 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
308 {
309 switch (pf) {
310 case PF_ARGB8888:
311 return DRM_FORMAT_ARGB8888;
312 case PF_RGBA8888:
313 return DRM_FORMAT_RGBA8888;
314 case PF_RGB888:
315 return DRM_FORMAT_RGB888;
316 case PF_RGB565:
317 return DRM_FORMAT_RGB565;
318 case PF_ARGB1555:
319 return DRM_FORMAT_ARGB1555;
320 case PF_ARGB4444:
321 return DRM_FORMAT_ARGB4444;
322 case PF_L8:
323 return DRM_FORMAT_C8;
324 case PF_AL44: /* No DRM support */
325 case PF_AL88: /* No DRM support */
326 case PF_NONE:
327 default:
328 return 0;
329 }
330 }
331
get_pixelformat_without_alpha(u32 drm)332 static inline u32 get_pixelformat_without_alpha(u32 drm)
333 {
334 switch (drm) {
335 case DRM_FORMAT_ARGB4444:
336 return DRM_FORMAT_XRGB4444;
337 case DRM_FORMAT_RGBA4444:
338 return DRM_FORMAT_RGBX4444;
339 case DRM_FORMAT_ARGB1555:
340 return DRM_FORMAT_XRGB1555;
341 case DRM_FORMAT_RGBA5551:
342 return DRM_FORMAT_RGBX5551;
343 case DRM_FORMAT_ARGB8888:
344 return DRM_FORMAT_XRGB8888;
345 case DRM_FORMAT_RGBA8888:
346 return DRM_FORMAT_RGBX8888;
347 default:
348 return 0;
349 }
350 }
351
ltdc_irq_thread(int irq,void * arg)352 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
353 {
354 struct drm_device *ddev = arg;
355 struct ltdc_device *ldev = ddev->dev_private;
356 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
357
358 /* Line IRQ : trigger the vblank event */
359 if (ldev->irq_status & ISR_LIF)
360 drm_crtc_handle_vblank(crtc);
361
362 /* Save FIFO Underrun & Transfer Error status */
363 mutex_lock(&ldev->err_lock);
364 if (ldev->irq_status & ISR_FUIF)
365 ldev->error_status |= ISR_FUIF;
366 if (ldev->irq_status & ISR_TERRIF)
367 ldev->error_status |= ISR_TERRIF;
368 mutex_unlock(&ldev->err_lock);
369
370 return IRQ_HANDLED;
371 }
372
ltdc_irq(int irq,void * arg)373 static irqreturn_t ltdc_irq(int irq, void *arg)
374 {
375 struct drm_device *ddev = arg;
376 struct ltdc_device *ldev = ddev->dev_private;
377
378 /* Read & Clear the interrupt status */
379 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
380 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
381
382 return IRQ_WAKE_THREAD;
383 }
384
385 /*
386 * DRM_CRTC
387 */
388
ltdc_crtc_update_clut(struct drm_crtc * crtc)389 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
390 {
391 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
392 struct drm_color_lut *lut;
393 u32 val;
394 int i;
395
396 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
397 return;
398
399 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
400
401 for (i = 0; i < CLUT_SIZE; i++, lut++) {
402 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
403 (lut->blue >> 8) | (i << 24);
404 reg_write(ldev->regs, LTDC_L1CLUTWR, val);
405 }
406 }
407
ltdc_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)408 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
409 struct drm_crtc_state *old_state)
410 {
411 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
412
413 DRM_DEBUG_DRIVER("\n");
414
415 /* Sets the background color value */
416 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
417
418 /* Enable IRQ */
419 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
420
421 /* Immediately commit the planes */
422 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
423
424 /* Enable LTDC */
425 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
426
427 drm_crtc_vblank_on(crtc);
428 }
429
ltdc_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)430 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
431 struct drm_crtc_state *old_state)
432 {
433 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
434
435 DRM_DEBUG_DRIVER("\n");
436
437 drm_crtc_vblank_off(crtc);
438
439 /* disable LTDC */
440 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
441
442 /* disable IRQ */
443 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
444
445 /* immediately commit disable of layers before switching off LTDC */
446 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
447 }
448
449 #define CLK_TOLERANCE_HZ 50
450
451 static enum drm_mode_status
ltdc_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)452 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
453 const struct drm_display_mode *mode)
454 {
455 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
456 int target = mode->clock * 1000;
457 int target_min = target - CLK_TOLERANCE_HZ;
458 int target_max = target + CLK_TOLERANCE_HZ;
459 int result;
460
461 result = clk_round_rate(ldev->pixel_clk, target);
462
463 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
464
465 /* Filter modes according to the max frequency supported by the pads */
466 if (result > ldev->caps.pad_max_freq_hz)
467 return MODE_CLOCK_HIGH;
468
469 /*
470 * Accept all "preferred" modes:
471 * - this is important for panels because panel clock tolerances are
472 * bigger than hdmi ones and there is no reason to not accept them
473 * (the fps may vary a little but it is not a problem).
474 * - the hdmi preferred mode will be accepted too, but userland will
475 * be able to use others hdmi "valid" modes if necessary.
476 */
477 if (mode->type & DRM_MODE_TYPE_PREFERRED)
478 return MODE_OK;
479
480 /*
481 * Filter modes according to the clock value, particularly useful for
482 * hdmi modes that require precise pixel clocks.
483 */
484 if (result < target_min || result > target_max)
485 return MODE_CLOCK_RANGE;
486
487 return MODE_OK;
488 }
489
ltdc_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)490 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
491 const struct drm_display_mode *mode,
492 struct drm_display_mode *adjusted_mode)
493 {
494 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
495 int rate = mode->clock * 1000;
496
497 /*
498 * TODO clk_round_rate() does not work yet. When ready, it can
499 * be used instead of clk_set_rate() then clk_get_rate().
500 */
501
502 clk_disable(ldev->pixel_clk);
503 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
504 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
505 return false;
506 }
507 clk_enable(ldev->pixel_clk);
508
509 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
510
511 return true;
512 }
513
ltdc_crtc_mode_set_nofb(struct drm_crtc * crtc)514 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
515 {
516 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
517 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
518 struct videomode vm;
519 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
520 u32 total_width, total_height;
521 u32 val;
522
523 drm_display_mode_to_videomode(mode, &vm);
524
525 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
526 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
527 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
528 vm.hfront_porch, vm.hback_porch, vm.hsync_len,
529 vm.vfront_porch, vm.vback_porch, vm.vsync_len);
530
531 /* Convert video timings to ltdc timings */
532 hsync = vm.hsync_len - 1;
533 vsync = vm.vsync_len - 1;
534 accum_hbp = hsync + vm.hback_porch;
535 accum_vbp = vsync + vm.vback_porch;
536 accum_act_w = accum_hbp + vm.hactive;
537 accum_act_h = accum_vbp + vm.vactive;
538 total_width = accum_act_w + vm.hfront_porch;
539 total_height = accum_act_h + vm.vfront_porch;
540
541 /* Configures the HS, VS, DE and PC polarities. Default Active Low */
542 val = 0;
543
544 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
545 val |= GCR_HSPOL;
546
547 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
548 val |= GCR_VSPOL;
549
550 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
551 val |= GCR_DEPOL;
552
553 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
554 val |= GCR_PCPOL;
555
556 reg_update_bits(ldev->regs, LTDC_GCR,
557 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
558
559 /* Set Synchronization size */
560 val = (hsync << 16) | vsync;
561 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
562
563 /* Set Accumulated Back porch */
564 val = (accum_hbp << 16) | accum_vbp;
565 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
566
567 /* Set Accumulated Active Width */
568 val = (accum_act_w << 16) | accum_act_h;
569 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
570
571 /* Set total width & height */
572 val = (total_width << 16) | total_height;
573 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
574
575 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
576 }
577
ltdc_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)578 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
579 struct drm_crtc_state *old_crtc_state)
580 {
581 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
582 struct drm_pending_vblank_event *event = crtc->state->event;
583
584 DRM_DEBUG_ATOMIC("\n");
585
586 ltdc_crtc_update_clut(crtc);
587
588 /* Commit shadow registers = update planes at next vblank */
589 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
590
591 if (event) {
592 crtc->state->event = NULL;
593
594 spin_lock_irq(&crtc->dev->event_lock);
595 if (drm_crtc_vblank_get(crtc) == 0)
596 drm_crtc_arm_vblank_event(crtc, event);
597 else
598 drm_crtc_send_vblank_event(crtc, event);
599 spin_unlock_irq(&crtc->dev->event_lock);
600 }
601 }
602
603 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
604 .mode_valid = ltdc_crtc_mode_valid,
605 .mode_fixup = ltdc_crtc_mode_fixup,
606 .mode_set_nofb = ltdc_crtc_mode_set_nofb,
607 .atomic_flush = ltdc_crtc_atomic_flush,
608 .atomic_enable = ltdc_crtc_atomic_enable,
609 .atomic_disable = ltdc_crtc_atomic_disable,
610 };
611
ltdc_crtc_enable_vblank(struct drm_crtc * crtc)612 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
613 {
614 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
615
616 DRM_DEBUG_DRIVER("\n");
617 reg_set(ldev->regs, LTDC_IER, IER_LIE);
618
619 return 0;
620 }
621
ltdc_crtc_disable_vblank(struct drm_crtc * crtc)622 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
623 {
624 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
625
626 DRM_DEBUG_DRIVER("\n");
627 reg_clear(ldev->regs, LTDC_IER, IER_LIE);
628 }
629
630 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
631 .destroy = drm_crtc_cleanup,
632 .set_config = drm_atomic_helper_set_config,
633 .page_flip = drm_atomic_helper_page_flip,
634 .reset = drm_atomic_helper_crtc_reset,
635 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
636 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
637 .enable_vblank = ltdc_crtc_enable_vblank,
638 .disable_vblank = ltdc_crtc_disable_vblank,
639 .gamma_set = drm_atomic_helper_legacy_gamma_set,
640 };
641
642 /*
643 * DRM_PLANE
644 */
645
ltdc_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)646 static int ltdc_plane_atomic_check(struct drm_plane *plane,
647 struct drm_plane_state *state)
648 {
649 struct drm_framebuffer *fb = state->fb;
650 u32 src_x, src_y, src_w, src_h;
651
652 DRM_DEBUG_DRIVER("\n");
653
654 if (!fb)
655 return 0;
656
657 /* convert src_ from 16:16 format */
658 src_x = state->src_x >> 16;
659 src_y = state->src_y >> 16;
660 src_w = state->src_w >> 16;
661 src_h = state->src_h >> 16;
662
663 /* Reject scaling */
664 if (src_w != state->crtc_w || src_h != state->crtc_h) {
665 DRM_ERROR("Scaling is not supported");
666 return -EINVAL;
667 }
668
669 return 0;
670 }
671
ltdc_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * oldstate)672 static void ltdc_plane_atomic_update(struct drm_plane *plane,
673 struct drm_plane_state *oldstate)
674 {
675 struct ltdc_device *ldev = plane_to_ltdc(plane);
676 struct drm_plane_state *state = plane->state;
677 struct drm_framebuffer *fb = state->fb;
678 u32 lofs = plane->index * LAY_OFS;
679 u32 x0 = state->crtc_x;
680 u32 x1 = state->crtc_x + state->crtc_w - 1;
681 u32 y0 = state->crtc_y;
682 u32 y1 = state->crtc_y + state->crtc_h - 1;
683 u32 src_x, src_y, src_w, src_h;
684 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
685 enum ltdc_pix_fmt pf;
686
687 if (!state->crtc || !fb) {
688 DRM_DEBUG_DRIVER("fb or crtc NULL");
689 return;
690 }
691
692 /* convert src_ from 16:16 format */
693 src_x = state->src_x >> 16;
694 src_y = state->src_y >> 16;
695 src_w = state->src_w >> 16;
696 src_h = state->src_h >> 16;
697
698 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
699 plane->base.id, fb->base.id,
700 src_w, src_h, src_x, src_y,
701 state->crtc_w, state->crtc_h,
702 state->crtc_x, state->crtc_y);
703
704 bpcr = reg_read(ldev->regs, LTDC_BPCR);
705 ahbp = (bpcr & BPCR_AHBP) >> 16;
706 avbp = bpcr & BPCR_AVBP;
707
708 /* Configures the horizontal start and stop position */
709 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
710 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
711 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
712
713 /* Configures the vertical start and stop position */
714 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
715 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
716 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
717
718 /* Specifies the pixel format */
719 pf = to_ltdc_pixelformat(fb->format->format);
720 for (val = 0; val < NB_PF; val++)
721 if (ldev->caps.pix_fmt_hw[val] == pf)
722 break;
723
724 if (val == NB_PF) {
725 DRM_ERROR("Pixel format %.4s not supported\n",
726 (char *)&fb->format->format);
727 val = 0; /* set by default ARGB 32 bits */
728 }
729 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
730
731 /* Configures the color frame buffer pitch in bytes & line length */
732 pitch_in_bytes = fb->pitches[0];
733 line_length = drm_format_plane_cpp(fb->format->format, 0) *
734 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
735 val = ((pitch_in_bytes << 16) | line_length);
736 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
737 LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
738
739 /* Specifies the constant alpha value */
740 val = CONSTA_MAX;
741 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
742
743 /* Specifies the blending factors */
744 val = BF1_PAXCA | BF2_1PAXCA;
745 if (!fb->format->has_alpha)
746 val = BF1_CA | BF2_1CA;
747
748 /* Manage hw-specific capabilities */
749 if (ldev->caps.non_alpha_only_l1 &&
750 plane->type != DRM_PLANE_TYPE_PRIMARY)
751 val = BF1_PAXCA | BF2_1PAXCA;
752
753 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
754 LXBFCR_BF2 | LXBFCR_BF1, val);
755
756 /* Configures the frame buffer line number */
757 val = y1 - y0 + 1;
758 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
759
760 /* Sets the FB address */
761 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
762
763 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
764 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
765
766 /* Enable layer and CLUT if needed */
767 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
768 val |= LXCR_LEN;
769 reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
770 LXCR_LEN | LXCR_CLUTEN, val);
771
772 ldev->plane_fpsi[plane->index].counter++;
773
774 mutex_lock(&ldev->err_lock);
775 if (ldev->error_status & ISR_FUIF) {
776 DRM_DEBUG_DRIVER("Fifo underrun\n");
777 ldev->error_status &= ~ISR_FUIF;
778 }
779 if (ldev->error_status & ISR_TERRIF) {
780 DRM_DEBUG_DRIVER("Transfer error\n");
781 ldev->error_status &= ~ISR_TERRIF;
782 }
783 mutex_unlock(&ldev->err_lock);
784 }
785
ltdc_plane_atomic_disable(struct drm_plane * plane,struct drm_plane_state * oldstate)786 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
787 struct drm_plane_state *oldstate)
788 {
789 struct ltdc_device *ldev = plane_to_ltdc(plane);
790 u32 lofs = plane->index * LAY_OFS;
791
792 /* disable layer */
793 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
794
795 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
796 oldstate->crtc->base.id, plane->base.id);
797 }
798
ltdc_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)799 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
800 const struct drm_plane_state *state)
801 {
802 struct drm_plane *plane = state->plane;
803 struct ltdc_device *ldev = plane_to_ltdc(plane);
804 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
805 int ms_since_last;
806 ktime_t now;
807
808 now = ktime_get();
809 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
810
811 drm_printf(p, "\tuser_updates=%dfps\n",
812 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
813
814 fpsi->last_timestamp = now;
815 fpsi->counter = 0;
816 }
817
818 static const struct drm_plane_funcs ltdc_plane_funcs = {
819 .update_plane = drm_atomic_helper_update_plane,
820 .disable_plane = drm_atomic_helper_disable_plane,
821 .destroy = drm_plane_cleanup,
822 .reset = drm_atomic_helper_plane_reset,
823 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
824 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
825 .atomic_print_state = ltdc_plane_atomic_print_state,
826 };
827
828 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
829 .prepare_fb = drm_gem_fb_prepare_fb,
830 .atomic_check = ltdc_plane_atomic_check,
831 .atomic_update = ltdc_plane_atomic_update,
832 .atomic_disable = ltdc_plane_atomic_disable,
833 };
834
ltdc_plane_create(struct drm_device * ddev,enum drm_plane_type type)835 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
836 enum drm_plane_type type)
837 {
838 unsigned long possible_crtcs = CRTC_MASK;
839 struct ltdc_device *ldev = ddev->dev_private;
840 struct device *dev = ddev->dev;
841 struct drm_plane *plane;
842 unsigned int i, nb_fmt = 0;
843 u32 formats[NB_PF * 2];
844 u32 drm_fmt, drm_fmt_no_alpha;
845 int ret;
846
847 /* Get supported pixel formats */
848 for (i = 0; i < NB_PF; i++) {
849 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
850 if (!drm_fmt)
851 continue;
852 formats[nb_fmt++] = drm_fmt;
853
854 /* Add the no-alpha related format if any & supported */
855 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
856 if (!drm_fmt_no_alpha)
857 continue;
858
859 /* Manage hw-specific capabilities */
860 if (ldev->caps.non_alpha_only_l1 &&
861 type != DRM_PLANE_TYPE_PRIMARY)
862 continue;
863
864 formats[nb_fmt++] = drm_fmt_no_alpha;
865 }
866
867 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
868 if (!plane)
869 return NULL;
870
871 ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
872 <dc_plane_funcs, formats, nb_fmt,
873 NULL, type, NULL);
874 if (ret < 0)
875 return NULL;
876
877 drm_plane_helper_add(plane, <dc_plane_helper_funcs);
878
879 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
880
881 return plane;
882 }
883
ltdc_plane_destroy_all(struct drm_device * ddev)884 static void ltdc_plane_destroy_all(struct drm_device *ddev)
885 {
886 struct drm_plane *plane, *plane_temp;
887
888 list_for_each_entry_safe(plane, plane_temp,
889 &ddev->mode_config.plane_list, head)
890 drm_plane_cleanup(plane);
891 }
892
ltdc_crtc_init(struct drm_device * ddev,struct drm_crtc * crtc)893 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
894 {
895 struct ltdc_device *ldev = ddev->dev_private;
896 struct drm_plane *primary, *overlay;
897 unsigned int i;
898 int ret;
899
900 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
901 if (!primary) {
902 DRM_ERROR("Can not create primary plane\n");
903 return -EINVAL;
904 }
905
906 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
907 <dc_crtc_funcs, NULL);
908 if (ret) {
909 DRM_ERROR("Can not initialize CRTC\n");
910 goto cleanup;
911 }
912
913 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
914
915 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
916 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
917
918 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
919
920 /* Add planes. Note : the first layer is used by primary plane */
921 for (i = 1; i < ldev->caps.nb_layers; i++) {
922 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
923 if (!overlay) {
924 ret = -ENOMEM;
925 DRM_ERROR("Can not create overlay plane %d\n", i);
926 goto cleanup;
927 }
928 }
929
930 return 0;
931
932 cleanup:
933 ltdc_plane_destroy_all(ddev);
934 return ret;
935 }
936
937 /*
938 * DRM_ENCODER
939 */
940
941 static const struct drm_encoder_funcs ltdc_encoder_funcs = {
942 .destroy = drm_encoder_cleanup,
943 };
944
ltdc_encoder_init(struct drm_device * ddev,struct drm_bridge * bridge)945 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
946 {
947 struct drm_encoder *encoder;
948 int ret;
949
950 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
951 if (!encoder)
952 return -ENOMEM;
953
954 encoder->possible_crtcs = CRTC_MASK;
955 encoder->possible_clones = 0; /* No cloning support */
956
957 drm_encoder_init(ddev, encoder, <dc_encoder_funcs,
958 DRM_MODE_ENCODER_DPI, NULL);
959
960 ret = drm_bridge_attach(encoder, bridge, NULL);
961 if (ret) {
962 drm_encoder_cleanup(encoder);
963 return -EINVAL;
964 }
965
966 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
967
968 return 0;
969 }
970
ltdc_get_caps(struct drm_device * ddev)971 static int ltdc_get_caps(struct drm_device *ddev)
972 {
973 struct ltdc_device *ldev = ddev->dev_private;
974 u32 bus_width_log2, lcr, gc2r;
975
976 /* at least 1 layer must be managed */
977 lcr = reg_read(ldev->regs, LTDC_LCR);
978
979 ldev->caps.nb_layers = max_t(int, lcr, 1);
980
981 /* set data bus width */
982 gc2r = reg_read(ldev->regs, LTDC_GC2R);
983 bus_width_log2 = (gc2r & GC2R_BW) >> 4;
984 ldev->caps.bus_width = 8 << bus_width_log2;
985 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
986
987 switch (ldev->caps.hw_version) {
988 case HWVER_10200:
989 case HWVER_10300:
990 ldev->caps.reg_ofs = REG_OFS_NONE;
991 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
992 /*
993 * Hw older versions support non-alpha color formats derived
994 * from native alpha color formats only on the primary layer.
995 * For instance, RG16 native format without alpha works fine
996 * on 2nd layer but XR24 (derived color format from AR24)
997 * does not work on 2nd layer.
998 */
999 ldev->caps.non_alpha_only_l1 = true;
1000 ldev->caps.pad_max_freq_hz = 90000000;
1001 if (ldev->caps.hw_version == HWVER_10200)
1002 ldev->caps.pad_max_freq_hz = 65000000;
1003 break;
1004 case HWVER_20101:
1005 ldev->caps.reg_ofs = REG_OFS_4;
1006 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1007 ldev->caps.non_alpha_only_l1 = false;
1008 ldev->caps.pad_max_freq_hz = 150000000;
1009 break;
1010 default:
1011 return -ENODEV;
1012 }
1013
1014 return 0;
1015 }
1016
ltdc_load(struct drm_device * ddev)1017 int ltdc_load(struct drm_device *ddev)
1018 {
1019 struct platform_device *pdev = to_platform_device(ddev->dev);
1020 struct ltdc_device *ldev = ddev->dev_private;
1021 struct device *dev = ddev->dev;
1022 struct device_node *np = dev->of_node;
1023 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL};
1024 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL};
1025 struct drm_crtc *crtc;
1026 struct reset_control *rstc;
1027 struct resource *res;
1028 int irq, ret, i, endpoint_not_ready = -ENODEV;
1029
1030 DRM_DEBUG_DRIVER("\n");
1031
1032 /* Get endpoints if any */
1033 for (i = 0; i < MAX_ENDPOINTS; i++) {
1034 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i],
1035 &bridge[i]);
1036
1037 /*
1038 * If at least one endpoint is -EPROBE_DEFER, defer probing,
1039 * else if at least one endpoint is ready, continue probing.
1040 */
1041 if (ret == -EPROBE_DEFER)
1042 return ret;
1043 else if (!ret)
1044 endpoint_not_ready = 0;
1045 }
1046
1047 if (endpoint_not_ready)
1048 return endpoint_not_ready;
1049
1050 rstc = devm_reset_control_get_exclusive(dev, NULL);
1051
1052 mutex_init(&ldev->err_lock);
1053
1054 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1055 if (IS_ERR(ldev->pixel_clk)) {
1056 DRM_ERROR("Unable to get lcd clock\n");
1057 return -ENODEV;
1058 }
1059
1060 if (clk_prepare_enable(ldev->pixel_clk)) {
1061 DRM_ERROR("Unable to prepare pixel clock\n");
1062 return -ENODEV;
1063 }
1064
1065 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1066 ldev->regs = devm_ioremap_resource(dev, res);
1067 if (IS_ERR(ldev->regs)) {
1068 DRM_ERROR("Unable to get ltdc registers\n");
1069 ret = PTR_ERR(ldev->regs);
1070 goto err;
1071 }
1072
1073 for (i = 0; i < MAX_IRQ; i++) {
1074 irq = platform_get_irq(pdev, i);
1075 if (irq < 0)
1076 continue;
1077
1078 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1079 ltdc_irq_thread, IRQF_ONESHOT,
1080 dev_name(dev), ddev);
1081 if (ret) {
1082 DRM_ERROR("Failed to register LTDC interrupt\n");
1083 goto err;
1084 }
1085 }
1086
1087 if (!IS_ERR(rstc)) {
1088 reset_control_assert(rstc);
1089 usleep_range(10, 20);
1090 reset_control_deassert(rstc);
1091 }
1092
1093 /* Disable interrupts */
1094 reg_clear(ldev->regs, LTDC_IER,
1095 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1096
1097 ret = ltdc_get_caps(ddev);
1098 if (ret) {
1099 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1100 ldev->caps.hw_version);
1101 goto err;
1102 }
1103
1104 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
1105
1106 /* Add endpoints panels or bridges if any */
1107 for (i = 0; i < MAX_ENDPOINTS; i++) {
1108 if (panel[i]) {
1109 bridge[i] = drm_panel_bridge_add(panel[i],
1110 DRM_MODE_CONNECTOR_DPI);
1111 if (IS_ERR(bridge[i])) {
1112 DRM_ERROR("panel-bridge endpoint %d\n", i);
1113 ret = PTR_ERR(bridge[i]);
1114 goto err;
1115 }
1116 }
1117
1118 if (bridge[i]) {
1119 ret = ltdc_encoder_init(ddev, bridge[i]);
1120 if (ret) {
1121 DRM_ERROR("init encoder endpoint %d\n", i);
1122 goto err;
1123 }
1124 }
1125 }
1126
1127 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1128 if (!crtc) {
1129 DRM_ERROR("Failed to allocate crtc\n");
1130 ret = -ENOMEM;
1131 goto err;
1132 }
1133
1134 ret = ltdc_crtc_init(ddev, crtc);
1135 if (ret) {
1136 DRM_ERROR("Failed to init crtc\n");
1137 goto err;
1138 }
1139
1140 ret = drm_vblank_init(ddev, NB_CRTC);
1141 if (ret) {
1142 DRM_ERROR("Failed calling drm_vblank_init()\n");
1143 goto err;
1144 }
1145
1146 /* Allow usage of vblank without having to call drm_irq_install */
1147 ddev->irq_enabled = 1;
1148
1149 return 0;
1150
1151 err:
1152 for (i = 0; i < MAX_ENDPOINTS; i++)
1153 drm_panel_bridge_remove(bridge[i]);
1154
1155 clk_disable_unprepare(ldev->pixel_clk);
1156
1157 return ret;
1158 }
1159
ltdc_unload(struct drm_device * ddev)1160 void ltdc_unload(struct drm_device *ddev)
1161 {
1162 struct ltdc_device *ldev = ddev->dev_private;
1163 int i;
1164
1165 DRM_DEBUG_DRIVER("\n");
1166
1167 for (i = 0; i < MAX_ENDPOINTS; i++)
1168 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1169
1170 clk_disable_unprepare(ldev->pixel_clk);
1171 }
1172
1173 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1174 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1175 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1176 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1177 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1178 MODULE_LICENSE("GPL v2");
1179