1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21
22 #include "stm32-adc-core.h"
23
24 /**
25 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
26 * @csr: common status register offset
27 * @eoc1: adc1 end of conversion flag in @csr
28 * @eoc2: adc2 end of conversion flag in @csr
29 * @eoc3: adc3 end of conversion flag in @csr
30 * @ier: interrupt enable register offset for each adc
31 * @eocie_msk: end of conversion interrupt enable mask in @ier
32 */
33 struct stm32_adc_common_regs {
34 u32 csr;
35 u32 eoc1_msk;
36 u32 eoc2_msk;
37 u32 eoc3_msk;
38 u32 ier;
39 u32 eocie_msk;
40 };
41
42 struct stm32_adc_priv;
43
44 /**
45 * stm32_adc_priv_cfg - stm32 core compatible configuration data
46 * @regs: common registers for all instances
47 * @clk_sel: clock selection routine
48 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
49 */
50 struct stm32_adc_priv_cfg {
51 const struct stm32_adc_common_regs *regs;
52 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
53 u32 max_clk_rate_hz;
54 };
55
56 /**
57 * struct stm32_adc_priv - stm32 ADC core private data
58 * @irq: irq(s) for ADC block
59 * @domain: irq domain reference
60 * @aclk: clock reference for the analog circuitry
61 * @bclk: bus clock common for all ADCs, depends on part used
62 * @vref: regulator reference
63 * @cfg: compatible configuration data
64 * @common: common data for all ADC instances
65 */
66 struct stm32_adc_priv {
67 int irq[STM32_ADC_MAX_ADCS];
68 struct irq_domain *domain;
69 struct clk *aclk;
70 struct clk *bclk;
71 struct regulator *vref;
72 const struct stm32_adc_priv_cfg *cfg;
73 struct stm32_adc_common common;
74 };
75
to_stm32_adc_priv(struct stm32_adc_common * com)76 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
77 {
78 return container_of(com, struct stm32_adc_priv, common);
79 }
80
81 /* STM32F4 ADC internal common clock prescaler division ratios */
82 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
83
84 /**
85 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
86 * @priv: stm32 ADC core private data
87 * Select clock prescaler used for analog conversions, before using ADC.
88 */
stm32f4_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)89 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
90 struct stm32_adc_priv *priv)
91 {
92 unsigned long rate;
93 u32 val;
94 int i;
95
96 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
97 if (!priv->aclk) {
98 dev_err(&pdev->dev, "No 'adc' clock found\n");
99 return -ENOENT;
100 }
101
102 rate = clk_get_rate(priv->aclk);
103 if (!rate) {
104 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
105 return -EINVAL;
106 }
107
108 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
109 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
110 break;
111 }
112 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
113 dev_err(&pdev->dev, "adc clk selection failed\n");
114 return -EINVAL;
115 }
116
117 priv->common.rate = rate / stm32f4_pclk_div[i];
118 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
119 val &= ~STM32F4_ADC_ADCPRE_MASK;
120 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
121 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
122
123 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
124 priv->common.rate / 1000);
125
126 return 0;
127 }
128
129 /**
130 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
131 * @ckmode: ADC clock mode, Async or sync with prescaler.
132 * @presc: prescaler bitfield for async clock mode
133 * @div: prescaler division ratio
134 */
135 struct stm32h7_adc_ck_spec {
136 u32 ckmode;
137 u32 presc;
138 int div;
139 };
140
141 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
142 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
143 { 0, 0, 1 },
144 { 0, 1, 2 },
145 { 0, 2, 4 },
146 { 0, 3, 6 },
147 { 0, 4, 8 },
148 { 0, 5, 10 },
149 { 0, 6, 12 },
150 { 0, 7, 16 },
151 { 0, 8, 32 },
152 { 0, 9, 64 },
153 { 0, 10, 128 },
154 { 0, 11, 256 },
155 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
156 { 1, 0, 1 },
157 { 2, 0, 2 },
158 { 3, 0, 4 },
159 };
160
stm32h7_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)161 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
162 struct stm32_adc_priv *priv)
163 {
164 u32 ckmode, presc, val;
165 unsigned long rate;
166 int i, div;
167
168 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
169 if (!priv->bclk) {
170 dev_err(&pdev->dev, "No 'bus' clock found\n");
171 return -ENOENT;
172 }
173
174 /*
175 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
176 * So, choice is to have bus clock mandatory and adc clock optional.
177 * If optional 'adc' clock has been found, then try to use it first.
178 */
179 if (priv->aclk) {
180 /*
181 * Asynchronous clock modes (e.g. ckmode == 0)
182 * From spec: PLL output musn't exceed max rate
183 */
184 rate = clk_get_rate(priv->aclk);
185 if (!rate) {
186 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
187 return -EINVAL;
188 }
189
190 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
191 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
192 presc = stm32h7_adc_ckmodes_spec[i].presc;
193 div = stm32h7_adc_ckmodes_spec[i].div;
194
195 if (ckmode)
196 continue;
197
198 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
199 goto out;
200 }
201 }
202
203 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
204 rate = clk_get_rate(priv->bclk);
205 if (!rate) {
206 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
207 return -EINVAL;
208 }
209
210 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
211 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
212 presc = stm32h7_adc_ckmodes_spec[i].presc;
213 div = stm32h7_adc_ckmodes_spec[i].div;
214
215 if (!ckmode)
216 continue;
217
218 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
219 goto out;
220 }
221
222 dev_err(&pdev->dev, "adc clk selection failed\n");
223 return -EINVAL;
224
225 out:
226 /* rate used later by each ADC instance to control BOOST mode */
227 priv->common.rate = rate / div;
228
229 /* Set common clock mode and prescaler */
230 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
231 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
232 val |= ckmode << STM32H7_CKMODE_SHIFT;
233 val |= presc << STM32H7_PRESC_SHIFT;
234 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
235
236 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
237 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
238
239 return 0;
240 }
241
242 /* STM32F4 common registers definitions */
243 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
244 .csr = STM32F4_ADC_CSR,
245 .eoc1_msk = STM32F4_EOC1,
246 .eoc2_msk = STM32F4_EOC2,
247 .eoc3_msk = STM32F4_EOC3,
248 .ier = STM32F4_ADC_CR1,
249 .eocie_msk = STM32F4_EOCIE,
250 };
251
252 /* STM32H7 common registers definitions */
253 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
254 .csr = STM32H7_ADC_CSR,
255 .eoc1_msk = STM32H7_EOC_MST,
256 .eoc2_msk = STM32H7_EOC_SLV,
257 .ier = STM32H7_ADC_IER,
258 .eocie_msk = STM32H7_EOCIE,
259 };
260
261 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
262 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
263 };
264
stm32_adc_eoc_enabled(struct stm32_adc_priv * priv,unsigned int adc)265 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
266 unsigned int adc)
267 {
268 u32 ier, offset = stm32_adc_offset[adc];
269
270 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
271
272 return ier & priv->cfg->regs->eocie_msk;
273 }
274
275 /* ADC common interrupt for all instances */
stm32_adc_irq_handler(struct irq_desc * desc)276 static void stm32_adc_irq_handler(struct irq_desc *desc)
277 {
278 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
279 struct irq_chip *chip = irq_desc_get_chip(desc);
280 u32 status;
281
282 chained_irq_enter(chip, desc);
283 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
284
285 /*
286 * End of conversion may be handled by using IRQ or DMA. There may be a
287 * race here when two conversions complete at the same time on several
288 * ADCs. EOC may be read 'set' for several ADCs, with:
289 * - an ADC configured to use DMA (EOC triggers the DMA request, and
290 * is then automatically cleared by DR read in hardware)
291 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
292 * be called in this case)
293 * So both EOC status bit in CSR and EOCIE control bit must be checked
294 * before invoking the interrupt handler (e.g. call ISR only for
295 * IRQ-enabled ADCs).
296 */
297 if (status & priv->cfg->regs->eoc1_msk &&
298 stm32_adc_eoc_enabled(priv, 0))
299 generic_handle_irq(irq_find_mapping(priv->domain, 0));
300
301 if (status & priv->cfg->regs->eoc2_msk &&
302 stm32_adc_eoc_enabled(priv, 1))
303 generic_handle_irq(irq_find_mapping(priv->domain, 1));
304
305 if (status & priv->cfg->regs->eoc3_msk &&
306 stm32_adc_eoc_enabled(priv, 2))
307 generic_handle_irq(irq_find_mapping(priv->domain, 2));
308
309 chained_irq_exit(chip, desc);
310 };
311
stm32_adc_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)312 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
313 irq_hw_number_t hwirq)
314 {
315 irq_set_chip_data(irq, d->host_data);
316 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
317
318 return 0;
319 }
320
stm32_adc_domain_unmap(struct irq_domain * d,unsigned int irq)321 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
322 {
323 irq_set_chip_and_handler(irq, NULL, NULL);
324 irq_set_chip_data(irq, NULL);
325 }
326
327 static const struct irq_domain_ops stm32_adc_domain_ops = {
328 .map = stm32_adc_domain_map,
329 .unmap = stm32_adc_domain_unmap,
330 .xlate = irq_domain_xlate_onecell,
331 };
332
stm32_adc_irq_probe(struct platform_device * pdev,struct stm32_adc_priv * priv)333 static int stm32_adc_irq_probe(struct platform_device *pdev,
334 struct stm32_adc_priv *priv)
335 {
336 struct device_node *np = pdev->dev.of_node;
337 unsigned int i;
338
339 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
340 priv->irq[i] = platform_get_irq(pdev, i);
341 if (priv->irq[i] < 0) {
342 /*
343 * At least one interrupt must be provided, make others
344 * optional:
345 * - stm32f4/h7 shares a common interrupt.
346 * - stm32mp1, has one line per ADC (either for ADC1,
347 * ADC2 or both).
348 */
349 if (i && priv->irq[i] == -ENXIO)
350 continue;
351 dev_err(&pdev->dev, "failed to get irq\n");
352
353 return priv->irq[i];
354 }
355 }
356
357 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
358 &stm32_adc_domain_ops,
359 priv);
360 if (!priv->domain) {
361 dev_err(&pdev->dev, "Failed to add irq domain\n");
362 return -ENOMEM;
363 }
364
365 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
366 if (priv->irq[i] < 0)
367 continue;
368 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
369 irq_set_handler_data(priv->irq[i], priv);
370 }
371
372 return 0;
373 }
374
stm32_adc_irq_remove(struct platform_device * pdev,struct stm32_adc_priv * priv)375 static void stm32_adc_irq_remove(struct platform_device *pdev,
376 struct stm32_adc_priv *priv)
377 {
378 int hwirq;
379 unsigned int i;
380
381 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
382 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
383 irq_domain_remove(priv->domain);
384
385 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
386 if (priv->irq[i] < 0)
387 continue;
388 irq_set_chained_handler(priv->irq[i], NULL);
389 }
390 }
391
stm32_adc_probe(struct platform_device * pdev)392 static int stm32_adc_probe(struct platform_device *pdev)
393 {
394 struct stm32_adc_priv *priv;
395 struct device *dev = &pdev->dev;
396 struct device_node *np = pdev->dev.of_node;
397 struct resource *res;
398 int ret;
399
400 if (!pdev->dev.of_node)
401 return -ENODEV;
402
403 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
404 if (!priv)
405 return -ENOMEM;
406
407 priv->cfg = (const struct stm32_adc_priv_cfg *)
408 of_match_device(dev->driver->of_match_table, dev)->data;
409
410 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
412 if (IS_ERR(priv->common.base))
413 return PTR_ERR(priv->common.base);
414 priv->common.phys_base = res->start;
415
416 priv->vref = devm_regulator_get(&pdev->dev, "vref");
417 if (IS_ERR(priv->vref)) {
418 ret = PTR_ERR(priv->vref);
419 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
420 return ret;
421 }
422
423 ret = regulator_enable(priv->vref);
424 if (ret < 0) {
425 dev_err(&pdev->dev, "vref enable failed\n");
426 return ret;
427 }
428
429 ret = regulator_get_voltage(priv->vref);
430 if (ret < 0) {
431 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
432 goto err_regulator_disable;
433 }
434 priv->common.vref_mv = ret / 1000;
435 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
436
437 priv->aclk = devm_clk_get(&pdev->dev, "adc");
438 if (IS_ERR(priv->aclk)) {
439 ret = PTR_ERR(priv->aclk);
440 if (ret == -ENOENT) {
441 priv->aclk = NULL;
442 } else {
443 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
444 goto err_regulator_disable;
445 }
446 }
447
448 if (priv->aclk) {
449 ret = clk_prepare_enable(priv->aclk);
450 if (ret < 0) {
451 dev_err(&pdev->dev, "adc clk enable failed\n");
452 goto err_regulator_disable;
453 }
454 }
455
456 priv->bclk = devm_clk_get(&pdev->dev, "bus");
457 if (IS_ERR(priv->bclk)) {
458 ret = PTR_ERR(priv->bclk);
459 if (ret == -ENOENT) {
460 priv->bclk = NULL;
461 } else {
462 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
463 goto err_aclk_disable;
464 }
465 }
466
467 if (priv->bclk) {
468 ret = clk_prepare_enable(priv->bclk);
469 if (ret < 0) {
470 dev_err(&pdev->dev, "adc clk enable failed\n");
471 goto err_aclk_disable;
472 }
473 }
474
475 ret = priv->cfg->clk_sel(pdev, priv);
476 if (ret < 0)
477 goto err_bclk_disable;
478
479 ret = stm32_adc_irq_probe(pdev, priv);
480 if (ret < 0)
481 goto err_bclk_disable;
482
483 platform_set_drvdata(pdev, &priv->common);
484
485 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
486 if (ret < 0) {
487 dev_err(&pdev->dev, "failed to populate DT children\n");
488 goto err_irq_remove;
489 }
490
491 return 0;
492
493 err_irq_remove:
494 stm32_adc_irq_remove(pdev, priv);
495
496 err_bclk_disable:
497 if (priv->bclk)
498 clk_disable_unprepare(priv->bclk);
499
500 err_aclk_disable:
501 if (priv->aclk)
502 clk_disable_unprepare(priv->aclk);
503
504 err_regulator_disable:
505 regulator_disable(priv->vref);
506
507 return ret;
508 }
509
stm32_adc_remove(struct platform_device * pdev)510 static int stm32_adc_remove(struct platform_device *pdev)
511 {
512 struct stm32_adc_common *common = platform_get_drvdata(pdev);
513 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
514
515 of_platform_depopulate(&pdev->dev);
516 stm32_adc_irq_remove(pdev, priv);
517 if (priv->bclk)
518 clk_disable_unprepare(priv->bclk);
519 if (priv->aclk)
520 clk_disable_unprepare(priv->aclk);
521 regulator_disable(priv->vref);
522
523 return 0;
524 }
525
526 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
527 .regs = &stm32f4_adc_common_regs,
528 .clk_sel = stm32f4_adc_clk_sel,
529 .max_clk_rate_hz = 36000000,
530 };
531
532 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
533 .regs = &stm32h7_adc_common_regs,
534 .clk_sel = stm32h7_adc_clk_sel,
535 .max_clk_rate_hz = 36000000,
536 };
537
538 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
539 .regs = &stm32h7_adc_common_regs,
540 .clk_sel = stm32h7_adc_clk_sel,
541 .max_clk_rate_hz = 40000000,
542 };
543
544 static const struct of_device_id stm32_adc_of_match[] = {
545 {
546 .compatible = "st,stm32f4-adc-core",
547 .data = (void *)&stm32f4_adc_priv_cfg
548 }, {
549 .compatible = "st,stm32h7-adc-core",
550 .data = (void *)&stm32h7_adc_priv_cfg
551 }, {
552 .compatible = "st,stm32mp1-adc-core",
553 .data = (void *)&stm32mp1_adc_priv_cfg
554 }, {
555 },
556 };
557 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
558
559 static struct platform_driver stm32_adc_driver = {
560 .probe = stm32_adc_probe,
561 .remove = stm32_adc_remove,
562 .driver = {
563 .name = "stm32-adc-core",
564 .of_match_table = stm32_adc_of_match,
565 },
566 };
567 module_platform_driver(stm32_adc_driver);
568
569 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
570 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
571 MODULE_LICENSE("GPL v2");
572 MODULE_ALIAS("platform:stm32-adc-core");
573